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Scalable high performance main memory system using phase-change memory technology
Abstract
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.
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Citations
Cited by
Kambatla, K., Kollias, G., Kumar, V., & Grama, A. (2014) · Journal of Parallel and Distributed Computing · doi:10.1016/j.jpdc.2014.01.003 · Cited by 819
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories
Balasubramonian, R., Kahng, A. B., Muralimanohar, N., Shafiee, A., & Srinivas, V. (2017) · ACM Transactions on Architecture and Code Optimization · doi:10.1145/3085572 · Cited by 559
In-Memory Big Data Management and Processing: A Survey
Zhang, H., Chen, G., Ooi, B. C., Tan, K.-L., & Zhang, M. (2015) · IEEE Transactions on Knowledge and Data Engineering · doi:10.1109/tkde.2015.2427795 · Cited by 414
Phase-Change Technology and the Future of Main Memory
Lee, B. C., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., & Burger, D. (2010) · IEEE Micro · doi:10.1109/mm.2010.24 · Cited by 395
Consistent and durable data structures for non-volatile byte-addressable memory
Venkataraman, S., Tolia, N. H., Ranganathan, P., & Campbell, R. H. (2011) · doi:10.5555/1960475.1960480 · Cited by 356
Metadata
- Authors
- Qureshi, M. K., Srinivasan, V., & Rivers, J. A.
- Venue
- Proceedings of the 36th annual international symposium on Computer architecture
- Publisher
- ACM
- Published
- 2009-06-20
- Pages
- 24-33
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W2048588974
- Cited by
- 1,277
- References
- 0
- FWCI
- 119.05
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Qureshi, M. K., Srinivasan, V., & Rivers, J. A. (2009). Scalable high performance main memory system using phase-change memory technology. Proceedings of the 36th annual international symposium on Computer architecture. https://doi.org/10.1145/1555754.1555760
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
