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Improving the ratio of memory operations to floating-point operations in loops
Open accessAbstract
Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed. To overcome these bottlenecks, programmers have learned to use a coding style that ensures a better balance between memory references and floating-point operations. In our view, this is a step in the wrong direction because it makes programs more machine-specific. A programmer should not be required to write a new program version for each new machine; instead, the task of specializing a program to a target machine should be left to the compiler. But is our view practical? Can a sophisticated optimizing compiler obviate the need for the myriad of programming tricks that have found their way into practice to improve the performance of the memory hierarchy? In this paper we attempt to answer that question. To do so, we develop and evaluate techniques that automatically restructure program loops to achieve high performance on specific target architectures. These methods attempt to balance computation and memory accesses and seek to eliminate or reduce pipeline interlock. To do this, they estimate statically the balance between memory operations and floating-point operations for each loop in a particular program and use these estimates to determine whether to apply various loop transformations. Experiments with our automatic techniques show that integer-factor speedups are possible on kernels. Additionally, the estimate of the balance between memory operations and computation, and the application of the estimate are very accurate—experiments reveal little difference between the balance achieved by our automatic system that is made possible by hand optimization.
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Lee, Y.-J., Diniz, P. C., Hall, M. W., & Lucas, R. F. (2005) · International Journal of Parallel Programming · doi:10.1007/s10766-005-3581-7 · Cited by 9
A case study using empirical optimization for a large, engineering application
Diniz, P. C., Lee, Y.-J., Hall, M. W., & Lucas, R. F. (2004) · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · doi:10.1109/ipdps.2004.1303225 · Cited by 9
Metadata
- Authors
- Carr, S., & Kennedy, K.
- Affiliations
- Michigan Technological University (US)
- Rice University (US)
- ORCID
- Carr, Steve
- Venue
- ACM Transactions on Programming Languages and Systems
- Published
- 1994-11
- Volume
- 16
- Issue
- 6
- Pages
- 1768-1810
- ISSN
- 0164-0925 (ISSN-L)
- 1558-4593
- OpenAlex
- W2138007781
- Cited by
- 155
- References
- 30
- Citations by year
- 2026: 2 · 2025: 5 · 2024: 3 · 2023: 1 · 2021: 1 · 2020: 1 · 2018: 1 · 2017: 1 · 2016: 2 · 2015: 2 · 2014: 4 · 2013: 1 · 2012: 8
- FWCI
- 3.90
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- ACM Transactions on Programming Languages and Systems (publishedVersion)
- Digital Commons - Michigan Tech (Michigan Technological University) (submittedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Software › Logic, programming, and type systems
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Keywords
- loop transformation, memory hierarchy, compiler optimization, floating-point performance, scientific kernels
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