Roofline: An Insightful Visual Performance Model for Floating-Point Programs and Multicore Architectures

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

The IBM Cell QS20 is a heterogeneous design with a relatively simple PowerPC core and eight SPEs that have their own unique SIMD-style instruction set and local memory instead of a cache.

“It is a heterogeneous design, with a relatively simple PowerPC core and with eight SPEs (Synergistic Processing Elements) that have their own unique SIMD-style instruction set.Each SPE also has its own local memory instead of a cache.”

May combine two claims.

For the 128^3 and 512^3 point 3-D FFT transforms examined, the operational intensities are 1.09 and 1.41, respectively.

“For the 128 3 -and 512 3 point transforms we examine, the operational intensities are 1.09 and 1.41, respectively.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The Sun UltraSPARC T2+ has the highest memory bandwidth of the four.

“It has the highest memory bandwidth of the four, for each chip has two dualchannel memory controllers that can drive four sets of DDR2/FBDIMMs.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The Sun T2+ keeps multiple memory transfers in flight by using many threads.

“It keeps multiple memory transfers in flight by using many threads.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The IBM Cell ridge point of operational intensity is 0.65.

“The IBM Cell ridge point of operational intensity is 0.65.”

May combine two claims.

The Sun T2+, with the lowest ridge point, was the easiest computer to program for these kernels, due to its large memory bandwidth and its easy-to-understand cores.

“The Sun T2+, with the lowest ridge point, was easiest to program, due to its large memory bandwidth and its easy-to-understand cores.”

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based). May combine two claims.

The Opteron X4 has a memory controller on chip, its own path to 667 MHz DDR2 DRAM, and separate paths for coherency.

“The Opteron X4 has a memory controller on chip, its own path to 667 MHz DDR2 DRAM, and separate paths for coherency.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

In Figure 1a, a kernel with operational intensity 2 is compute bound and a kernel with operational intensity 1 is memory bound.

“In Figure 1a, a kernel with operational intensity 2 is compute bound and a kernel with operational intensity 1 is memory bound.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The IBM Cell QS20 has the highest clock rate of the four multicores at 3.2 GHz.

“The clock rate of IBM Cell QS20 is highest of the four multicores at 3.2 GHz.”

May combine two claims.

Figure 2b shows memory bandwidth ceilings of 11 GBytes/sec without software prefetching, 4.8 GBytes/sec without memory affinity optimizations as well, and 2.7 GBytes/sec with only unit stride optimizations.

“Figure 2b shows the memory bandwidth ceilings of 11 GBytes/sec without software prefetching, 4.8 GBytes/sec without memory affinity optimizations as well, and 2.7 GBytes/sec with only unit stride optimizations.”

May combine two claims.

Both x86 multicores offer the no-allocate store cache optimization, and Cell does not have this problem since it uses DMA; hence T2+ is the only one with the lower intensity of 0.70.

“Both x86 multicores offer this cache optimization, and Cell does not have this problem since it uses DMA.Hence, T2+ is the only one with the lower intensity of 0.70.”

May combine two claims.

The Intel Xeon's peak double precision performance can be achieved only with operational intensities of at least 6.7, or balance requires 55 floating-point operations for every double precision operand (8 bytes) going to DRAM.

“However, the Roofline model in Figure 3a shows that this can be achieved only with operational intensities of at least 6.7; started alternatively, balance requires 55 floatingpoint operations for every double precision operand (8 bytes) going to DRAM.”

May combine two claims.

On Xeon and X4, an entire 128x128 plane fits in cache, increasing temporal locality and improving the operational intensity to 1.64 for the 128^3-point 3-D FFT.

“On Xeon and X4, an entire 128x128 plane fits in cache, increasing temporal locality and improving the intensity to 1.64 for the 128 3 -point transform.”

May combine two claims.

The paper develops Roofline models for 4 recent multicore computers and optimizes 4 floating-point kernels, and shows that the ceilings and rooflines bound the achieved results for all computers and kernels.

“To demonstrate the utility of the model, we develop Roofline models for 4 recent multicore computers and then optimize 4 floating-point kernels.We then show that the ceilings and rooflines bound the achieved results for all computers and kernels.”

• AssumptionRests on an assumption: For the four kernels, there is sufficient parallelism to utilize all the cores and threads and to keep them load balanced.

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based). May combine two claims.

For most kernels, achieving parity between multiplies and additions is very difficult, but for a few, parity is natural.

“For most kernels, achieving parity between multiplies and additions is very difficult, but for a few, parity is natural.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The four multicore computers in Table 1 are all dual-socket systems.

“Table 1 lists the key characteristics of the four multicore computers of this section, which are all dual-socket systems.”

May combine two claims.

The Sun T2+ has the highest memory bandwidth, so its ridge point is an exceptionally low operational intensity of just 0.33 Flops per byte.

“The Sun T2+ has the highest memory bandwidth so the ridge point is an exceptionally low operational intensity of just 0.33 Flops per byte.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The Opteron X4 is the only computer of the four with on-chip L3 caches.

“The Opteron X4 also uses sophisticated cores with high peak floating-point performance, but it is the only computer of the four with on-chip L3 caches.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The computational optimizations and the memory bandwidth optimizations overlap in the middle of Figure 2c.

“The middle of Figure 2c shows that the computational optimizations and the memory bandwidth optimizations overlap.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The Intel Xeon is the only one of the four machines with a front side bus connecting to a common north bridge chip and memory controller.

“It is the only one of the four machines with a front side bus connecting to a common north bridge chip and memory controller.”

Probably not a substantial claim: may not pass S3 (load-bearing).

Sparse matrix-vector multiplication is an example where parity between multiplies and additions is natural.

“One example is sparse matrix-vector multiplication.”

May combine two claims.

The Flops to byte ratio of LBMHD is 0.70 versus 0.25 or less in SpMV.

“The Flops to byte ratio is 0.70 versus 0.25 or less in SpMV.”

Probably not a substantial claim: may not pass S3 (load-bearing).

If the working set is small enough for the hardware to filter, the snoop filter nearly doubles the delivered memory bandwidth.

“If the working set is small enough for the hardware to filter, the snoop filter nearly doubles the delivered memory bandwidth.”

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based).

There are kernels where operational intensity increases with problem size, such as Dense Matrix and FFT problems.

“For example, there are kernels where the operational intensity increases with problem size, such as for Dense Matrix and FFT problems.”

May combine two claims.

The system modeled in Figure 1a has a peak double precision floating-point performance of 17.6 GFlops/sec and a peak memory bandwidth of 15 GBytes/sec from the paper's benchmark.

“The system being modeled has a peak double precision floating-point performance of 17.6 GFlops/sec and a peak memory bandwidth of 15 GBytes/sec from our benchmark.”

Probably not a substantial claim: may not pass S3 (load-bearing).

One exchange involves reading and writing 16 bytes, so its operational intensity is 1/32.

“One exchange involves reading and writing 16 bytes, so its operational intensity is 1/32.”

May combine two claims.

The ceilings are measured once, but they can be reordered depending on whether the multiplies and adds are naturally balanced or not in the kernel.

“The ceilings are measured once, but they can be reordered depending whether the multiplies and adds are naturally balanced or not in the kernel (see Section 4).”

May combine two claims.

All 16 kernel-computer cases validate the Roofline bound and bottleneck model, since the upper and lower ceilings bound performance and the kernels were optimized as the lower ceilings suggest.

“All 16 cases validate this bound and bottleneck model since the upper and lower ceilings of Roofline bound performance and the kernels were optimized as the lower ceilings suggest.”

May combine two claims.

With a ridge point close to the Xeon, the Opteron X4 was about as much effort to program, since it benefited from the most types of optimizations.

“With a ridge point close to the Xeon, the Opteron X4 was about as much effort, since the Opteron X4 benefited from the most types of optimizations.”

May combine two claims.

The operational ridge points for the two x86 computers were 4.4 and 6.7, meaning 35 to 55 Flops per 8-byte operand that accesses DRAM.

“The operational ridge points for the two x86 computers were 4.4 and 6.7-meaning 35 to 55 Flops per 8-byte operand that accesses DRAM”

May combine two claims.

Cell offered the highest performance on these kernels, but T2+ was the easiest computer on which to achieve its highest performance.

“Cell offered the highest performance on these kernels, but T2+ was the easiest computer on which to achieve its highest performance.”

May combine two claims.

The Sun T2+'s L2 cache was only 16-way set associative, which can lead to conflict misses when 64 threads access the cache, as it did for Stencil.

“The downside was that the L2 cache was only 16-way set associative, which can lead to conflict misses when 64 threads access the cache, as it did for Stencil.”

May combine two claims.

For the examples in this paper, the amount of integer code and the integer performance can affect performance.

“For the examples in this paper, the amount of integer code and the integer performance can affect performance.”

May combine two claims. The quote only partly states this claim.

The IBM Cell, with a ridge point almost as low as the Sun T2+, provided two types of challenges: awkward compilation for SIMD instructions and a more challenging memory system.

“The IBM Cell, with a ridge point almost as low as the Sun T2+, provided two types of challenges.”

May combine two claims.

The cache-hit rates of the three multicores with on-chip caches are at least 94% for stencil and 98% for FFT.

“For example, the cache-hit rates of our three multicores with on-chip caches are at least 94% for stencil and 98% for FFT.”

Probably not a substantial claim: may not pass S3 (load-bearing).

It was awkward to compile for the SIMD instructions of Cell's SPE, so at times the authors needed to help the compiler by inserting intrinsic statements with assembly language instructions into the C code.

“First, it was awkward to compile for the SIMD instructions of Cell's SPE, so at times we needed to help the compiler by inserting intrinsic statements with assembly language instructions into the C code.”

May combine two claims. The quote only partly states this claim.

For 3-D FFT, the surrounding ceilings are memory bound for Xeon and X4 but compute bound for T2+ and Cell.

“For FFT, interestingly, the surrounding ceilings are memory bound for Xeon and X4 but compute bound for T2+ and Cell.”

May combine two claims.

The metric limiting performance is memory bound in 15 of 16 ceilings for Xeon and X4, while it is almost evenly split between memory and compute bound for T2+ and Cell.

“The metric that limits performance is in bold: 15 of 16 ceilings are memory bound for Xeon and X4 while it's almost evenly split for T2+ and Cell.”

Probably not a substantial claim: may not pass S3 (load-bearing).

It was not easy to create the fastest version of these numerical methods on the divergent multicore architectures presented here.

“Our experience, however, is that it was not easy to create the fastest version of these numerical methods on the divergent multicore architectures presented here.”

May combine two claims.

Autotuning three of the four kernels gets very close to the compulsory memory traffic; the resultant working set is sometimes only a small fraction of the cache.

“Autotuning three of the four kernels gets very close to the compulsory memory traffic; in fact, the resultant working set is sometimes only a small fraction of the cache.”

Probably not a substantial claim: may not pass S3 (load-bearing).

Three of the results were considered significant enough to be accepted for publication at major conferences.

“Indeed, three of the results were considered significant enough to be accepted for publication at major conferences [12][25] [26].”

• cites [12][25][26]Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

The Intel Xeon was difficult to program because it was hard to understand the memory behavior of the dual front side buses, hard to understand how hardware prefetching worked, and because of the difficulty of getting good SIMD code from the compiler.

“The Intel Xeon was difficult because it was hard to understand the memory behavior of the dual front side buses, hard to understand how hardware prefetching worked, and because of the difficulty of getting good SIMD code from the compiler.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The memory behavior of the Opteron X4 was easier to understand than that of the Xeon.

“However, the memory behavior of the Opteron X4 was easier to understand than that of the Xeon.”

Probably not a substantial claim: may not pass S3 (load-bearing).

Like the Roofline, the ceilings only need be measured once per multicore computer.

“The good news is that like the Roofline, the ceilings only need be measured once per multicore computer.”

Probably not a substantial claim: may not pass S3 (load-bearing).

Computational ceilings can come from an optimization manual.

“Like the computational Roofline, the computational ceilings can come from an optimization manual [2], although it's easy to imagine collecting the necessary parameters from simple microbenchmarks.”

• cites [2] 2. AMD, Software Optimization Guide for AMD Family 10h Processors, Publication 40546, April 2008.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Classified as probably not a substantial claim.

Operational intensity suggests the DRAM bandwidth needed by a kernel on a particular computer.

“Thus, operational intensity suggests the DRAM bandwidth needed by a kernel on a particular computer.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Cell's 1 GB main memory is too small to hold 512^3 points, so the 512^3 operational intensity result is estimated.

“(Cell's 1 GB main memory is too small to hold 512 3 points, so we estimate this result.)”

Probably not a substantial claim: may not pass S3 (load-bearing).

A Roofline can be used repeatedly on different kernels because it does not vary.

“Given a Roofline, you can use it repeatedly on different kernels, since the Roofline doesn't vary.”

Classified as probably not a substantial claim.

The x-coordinate of the ridge point is the minimum operational intensity required to achieve maximum performance.

“The x-coordinate of the ridge point is the minimum operational intensity required to achieve maximum performance.”

Classified as probably not a substantial claim.

The height of the gap between a ceiling and the next higher one is the potential reward for trying that optimization.

“The height of the gap between a ceiling and the next higher one is the potential reward for trying that optimization.”

Probably not a substantial claim: may not pass S2 (checkable). May combine two claims.

The dwarfs will be important to computing in most current and future applications, so designers are advised to make sure they run well on systems they create.

“The claim is that they will be important to computing in most current and future applications, so designers are advised to make sure they run well on systems that they create, whether or not their creations are parallel.”

• cites [4] 4. K. Asanovic, R. Bodik, B. Catanzaro, J. Gebis, K. Keutzer, D. Patterson, W. Plishker, J. Shalf, S. Williams, K. Yelick. "The landscape of parallel computing research: A view from Berkeley." Tech. Rep. UCB/EECS-2006-183, EECS, U.C. Berkeley, Dec 2006.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Figure 2 suggests that optimization 1, which improves ILP/SIMD, has a large potential benefit for improving computation on that computer, and optimization 4, which improves memory affinity, has a large potential benefit for improving memory bandwidth on that computer.

“Thus, Figure 2 suggests that optimization 1, which improves ILP/SIMD, has a large potential benefit for improving computation on that computer, and optimization 4, which improves memory affinity, has a large potential benefit for improving memory bandwidth on that computer.”

May combine two claims.

The operational intensity of LBMHD is high enough that both computational and memory bandwidth optimizations make sense on all multicores but the T2+, whose Roofline ridge point is below that of LBMHD.

“Figures 3 and4 show that the operational intensity of LBMHD is high enough that both computational and memory bandwidth optimizations make sense on all multicores but the T2+, whose Roofline ridge point is below that of LBMHD.”

• AssumptionRests on an assumption: LBMHD tends to get a small fraction of peak performance on uniprocessors because of the complexity of the data structures and the irregularity of memory access patterns.

May combine two claims.

Memory traffic from conflict and capacity misses can considerably lower the operational intensity of a kernel, so such misses should be eliminated.

“Memory traffic from conflict and capacity misses can considerably lower the operational intensity of a kernel, so we should try to eliminate such misses.”

Probably not a substantial claim: may not pass S3 (load-bearing).

For sparse matrix-vector multiplication, floating-point mix should be placed as the lowest ceiling because it is inherent.

“For that domain, we would place floating-point mix as the lowest ceiling, since it is inherent.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The ridge point suggests the level of difficulty for programmers and compiler writers to achieve peak performance.

“As we shall see (Section 6.3.5), the ridge point suggests the level of difficulty for programmers and compiler writers to achieve peak performance.”

May combine two claims.

Caches affect the number of accesses that go to memory, so optimizations that improve cache performance increase operational intensity.

“Clearly, caches affect the number of accesses that go to memory, so optimizations that improve cache performance increase operational intensity.”

May combine two claims.

If the ridge point is far to the right, only kernels with very high operational intensity can achieve the maximum performance of that computer; if far to the left, almost any kernel can potentially hit the maximum performance.

“If the ridge point is far to the right, then only kernels with very high operational intensity can achieve the maximum performance of that computer.If it is far to the left, then almost any kernel can potentially hit the maximum performance.”

May combine two claims.

The Opteron X2 and Opteron X4 share the same socket, so they have the same DRAM channels and can have the same peak memory bandwidth, although prefetching is better in the X4.

“To simplify board design, they share the same socket.Hence, they have the same DRAM channels and can thus have the same peak memory bandwidth, although the prefetching is better in the X4.”

Probably not a substantial claim: may not pass S3 (load-bearing).

The Seven Dwarfs are seven numerical methods identified by Phil Colella as important for science and engineering for at least the next decade.

“This expert in scientific computing has identified seven numerical methods that he believes will be important for science and engineering for at least the next decade.Because he picked seven, they have become known as the Seven Dwarfs.”

• cites [10] 10. P. Colella, "Defining Software Requirements for Scientific Computing," presentation, 2004.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S3 (load-bearing).

Memory ceilings require running experiments on each computer to determine the gap between them.

“The memory ceilings require running experiments on each computer to determine the gap between them (see Appendix A.1).”

May combine two claims.

A kernel whose operational intensity hits the flat part of the roof is compute bound; one that hits the slanted part is memory bound.

“If we think of operational intensity as a column that hits the roof, either it hits the flat part of the roof, which means performance is compute bound, or it hits the slanted part of the roof, which means performance is ultimately memory bound.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Kernel 1's vertical line falls below the floating-point imbalance optimization, so optimization 2 may be skipped.

“Note that the Kernel 1 vertical lines falls below the floating-point imbalance optimization, so optimization 2 may be skipped.”

May combine two claims.

The operational intensity of a kernel determines the optimization region and thus which optimizations to try.

“The operational intensity of a kernel determines the optimization region, and thus which optimizations to try.”

Probably not a substantial claim: may not pass S3 (load-bearing).

If a kernel fell in the yellow triangle on the lower left, the model would suggest trying just memory optimizations.

“If a kernel fell in the yellow triangle on the lower left, the model would suggest trying just memory optimizations.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Kernel 2 falls in the blue trapezoid on the right, which suggests working only on the computational optimizations.

“For example, Kernel 2 falls in the blue trapezoid on the right, which suggests working only on the computational optimizations.”

May combine two claims.

The high ratio for Intel Xeon is due in part to the limitation of the front side bus, which also carries coherency traffic that can consume half the bus bandwidth.

“This high ratio is due in part to the limitation of the front side bus, which also carries coherency traffic that can consume half the bus bandwidth.”

Classified as probably not a substantial claim.

Operational intensity tells us which ceilings to look at.

“Operational intensity tells us which ceilings to look at.”

May combine two claims.

Compulsory misses set the minimum memory traffic and hence the highest possible operational intensity.

“Compulsory misses set the minimum memory traffic and hence the highest possible operational intensity.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Kernel 1 falls in the green parallelogram in the middle, which suggests trying both types of optimizations.

“Kernel 1 falls in the green (= yellow + blue) parallelogram in the middle, which suggests trying both types of optimizations.”

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based). May combine two claims.

The order of the ceilings suggests the optimization order, so ceilings are ranked from bottom to top: those most likely to be realized by a compiler or with little effort by a programmer are at the bottom and those difficult to implement or inherently lacking in a kernel are at the top.

“The order of the ceilings suggest the optimization order, so we rank the ceilings from bottom to top: those most likely to be realized by a compiler or with little effort by a programmer are at the bottom and those that are difficult to be implemented by a programmer or inherently lacking in a kernel are at the top.”

Probably not a substantial claim: may not pass S2 (checkable), S3 (load-bearing), S4 (based).

There may be a synergistic relationship between performance counters and the Roofline model.

“In fact, we believe there may be a synergistic relationship between performance counters and the Roofline model.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

Relative to other computers, the Sun T2+ executes more integer instructions and executes them at a lower rate, which hurts overall performance.

“Relative to others, T2+ executes more integer instructions and executes them at a lower rate, which hurts overall performance.”

• AssumptionRests on an assumption: The Sun UltraSPARC T2+ fetches two instructions per core per clock cycle and lacks the x86 SIMD instructions that can operate on two double-precision floating-point operands at a time.

Probably not a substantial claim: may not pass S3 (load-bearing).

The heights of the ceilings in this paper document the maximum potential gain of a code performing this optimization.

“Note that the heights of the ceilings in this paper document the maximum potential gain of a code performing this optimization.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

If the working set fits in the L2 cache, the diagonal Roofline could be L2 cache bandwidth instead of DRAM bandwidth, and the operational intensity on the X-axis would be based on Flops per L2 cache byte accessed.

“If the working set fits in the L2 cache, the diagonal Roofline could be L2 cache bandwidth instead of DRAM bandwidth, and the operational intensity on the X-axis would be based on Flops per L2 cache byte accessed.”

Probably not a substantial claim: may not pass S3 (load-bearing).

Jike Chong used the Roofline model to keep track of the platforms' peak arithmetic throughput and L1, L2, and DRAM bandwidths.

“He used the Roofline model to keep track the platforms' peak arithmetic throughput and L1, L2, and DRAM bandwidths.”

• cites [9] 9. J. Chong, Private Communication, 2008.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based).

The Roofline model can work for other kernels where the performance is a function of different performance metrics.

“However, we believe the Roofline model can work for other kernels where the performance was a function of different performance metrics.”

May combine two claims.

For option pricing with an explicit PDE formulation, the working set is too large to fit into cache, and the Roofline model helps to indicate the extent to which cache blocking is necessary to extract peak arithmetic performance.

“For option pricing with an explicit PDE formulation, the working set is too large to fit into cache, and the Roofline model helps to indicate the extent to which cache blocking is necessary to extract peak arithmetic performance.”

• cites [9] 9. J. Chong, Private Communication, 2008.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S3 (load-bearing).

Jike Chong ported two financial PDE solvers to four other multicore computers: the Intel Penryn and Larrabee and NVIDIA G80 and GTX280.

“For example, Jike Chong ported two financial PDE solvers to four other multicore computers: the Intel Penryn and Larrabee and NVIDIA G80 and GTX280.[9]”

• cites [9] 9. J. Chong, Private Communication, 2008.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

May combine two claims.

The diagonal memory performance line would move up, and the ridge point would move to the left.

“The diagonal memory performance line would move up, and the ridge point would surely move to the left.”

Probably not a substantial claim: may not pass S2 (checkable), S3 (load-bearing).

The requirements for automatic creation of a Roofline model could guide the designer as to which metrics should be collected when faced with hundreds of candidates but a limited hardware budget.

“The requirements for automatic creation of a Roofline model could guide the designer as to which metrics should be collected when faced with literally hundreds of candidates but a limited hardware budget.[6]”

• cites [6] 6. S. Bird et al, "A Case for Sensible Performance Counters," submitted to the First USENIX Workshop on Hot Topics in Parallelism (HotPar '09), Berkeley CA, March 2009.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

Probably not a substantial claim: may not pass S2 (checkable), S3 (load-bearing), S4 (based). May combine two claims.

Roofline models can offer insights to other types of multicore systems such as vector processors and GPUs; other kernels such as sort and ray tracing; other computational metrics such as pair-wise sorts per second and frames per second; and other traffic metrics such as L3 cache bandwidth and I/O bandwidth.

“We believe Roofline models can offer insights to other types of multicore systems such as vector processors and GPUs (Graphical Processing Units); other kernels such as sort and ray tracing; other computational metrics such as pair-wise sorts per second and frames per second; and other traffic metrics such as L3 cache bandwidth and I/O bandwidth.”

May combine two claims.

Increasing cache size helps only with capacity misses and possibly conflict misses, so a larger cache can have no effect on the operational intensity for the three autotuned kernels.

“Increasing cache size helps only with capacity misses and possibly conflict misses, so a larger cache can have no effect on the operational intensity for those three kernels.”

Probably not a substantial claim: may not pass S2 (checkable). May combine two claims.

Just the graphical Roofline offers insights into the difficulty of achieving the peak performance of a computer, as it makes obvious when a computer is imbalanced.

“Just the graphical Roofline offers insights into the difficulty of achieving the peak performance of a computer, as it makes obvious when a computer is imbalanced.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

The roofline and ceilings were measured using microbenchmarks, but performance counters could have been used.

“We measured the roofline and ceilings using microbenchmarks, but we could have used performance counters (see Appendix A.1 and A.3).”

Probably not a substantial claim: may not pass S3 (load-bearing), S4 (based). May combine two claims.

DMA for a local store is easier to program, to achieve good memory performance, and to overlap with computation than prefetching to caches.

“DMA for a local store is easier to program, to achieve good memory performance, and to overlap with computation than prefetching to caches.”

Probably not a substantial claim: may not pass S2 (checkable), S3 (load-bearing).

The sea change from sequential computing to parallel computing is increasing the diversity of computers that programmers must confront in making correct, efficient, scalable, and portable software.

“The sea change from sequential computing to parallel computing is increasing the diversity of computers that programmers must confront in making correct, efficient, scalable, and portable software [4].”

• cites [4] 4. K. Asanovic, R. Bodik, B. Catanzaro, J. Gebis, K. Keutzer, D. Patterson, W. Plishker, J. Shalf, S. Williams, K. Yelick. "The landscape of parallel computing research: A view from Berkeley." Tech. Rep. UCB/EECS-2006-183, EECS, U.C. Berkeley, Dec 2006.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.

May combine two claims.

While the bandwidth orientation of the Roofline model works for uniprocessors, it is even more helpful for multicores.

“While the bandwidth orientation of the Roofline model certainly works for uniprocessors, it is even more helpful for multicores.”

Probably not a substantial claim: may not pass S2 (checkable), S3 (load-bearing). May combine two claims.

The awkwardness of compiling for Cell's SPE SIMD instructions reflects the immaturity of the IBM compiler as well as the difficulty of compiling for these SIMD instructions.

“This comment reflects the immaturity of the IBM compiler as well as the difficulty of compiling for these SIMD instructions.”

Probably not a substantial claim: may not pass S3 (load-bearing). May combine two claims.

For the option-pricing problem with an implicit PDE solver, the working set is small enough to fit into L1 and the L1 bandwidth is sufficient to support peak arithmetic throughput, so the Roofline model indicates that no optimization is necessary.

“Specifically, for the option-pricing problem with an implicit PDE solver, the working set is small enough to fit into L1 and the L1 bandwidth is sufficient to support peak arithmetic throughput, so the Roofline model indicates that no optimization is necessary.”

• cites [9] 9. J. Chong, Private Communication, 2008.Not matched

  Couldn’t be matched to a paper in Crossref, so it can’t be checked.