The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
A scalable processing-in-memory accelerator for parallel graph processing
Abstract
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations.
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Cites
The anatomy of a large-scale hypertextual Web search engine
Brin, S., & Page, L. (1998) · Computer Networks and ISDN Systems · doi:10.1016/s0169-7552(98)00110-x · Cited by 16,004
Measurement and analysis of online social networks
Mislove, A., Marcon, M., Gummadi, K. P., Druschel, P., & Bhattacharjee, B. (2007) · Proceedings of the 7th ACM SIGCOMM conference on Internet measurement · doi:10.1145/1298306.1298311 · Cited by 3,057
Cited by
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Song, L., Qian, X., Li, H., & Chen, Y. (2017) · 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2017.55 · Cited by 833
Lee, S., Kang, S.-H., Lee, J., Kim, H., Lee, E., Seo, S., Yoon, H., Lee, S., Lim, K., Shin, H., et al. (2021) · 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca52012.2021.00013 · Cited by 269
Practical Near-Data Processing for In-Memory Analytics Frameworks
Gao, M., Ayers, G., & Kozyrakis, C. (2015) · 2015 International Conference on Parallel Architecture and Compilation (PACT) · doi:10.1109/pact.2015.22 · Cited by 266
In-Memory Data Parallel Processor
Fujiki, D., Mahlke, S., & Das, R. (2018) · Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems · doi:10.1145/3173162.3173171 · Cited by 109
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training
Imani, M., Yin, X., Messerly, J., Gupta, S., Niemier, M., Hu, X. S., & Rosing, T. (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2952544 · Cited by 87
Metadata
- Authors
- Ahn, J., Hong, S., Yoo, S., Mutlu, O., & Choi, K.
- Venue
- Proceedings of the 42nd Annual International Symposium on Computer Architecture
- Publisher
- ACM
- Published
- 2015-06-13
- Pages
- 105-117
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W1981943579
- Cited by
- 767
- References
- 2
- FWCI
- 33.53
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Ahn, J., Hong, S., Yoo, S., Mutlu, O., & Choi, K. (2015). A scalable processing-in-memory accelerator for parallel graph processing. Proceedings of the 42nd Annual International Symposium on Computer Architecture. https://doi.org/10.1145/2749469.2750386
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