The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
Data reorganization in memory using 3D-stacked DRAM
Abstract
In this paper we focus on common data reorganization operations such as shuffle, pack/unpack, swap, transpose, and layout transformations. Although these operations simply relocate the data in the memory, they are costly on conventional systems mainly due to inefficient access patterns, limited data reuse and roundtrip data traversal throughout the memory hierarchy. This paper presents a two pronged approach for efficient data reorganization, which combines (i) a proposed DRAM-aware reshape accelerator integrated within 3D-stacked DRAM, and (ii) a mathematical framework that is used to represent and optimize the reorganization operations.
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Cites
The Design and Implementation of FFTW3
Frigo, M., & Johnson, S. G. (2005) · Proceedings of the IEEE · doi:10.1109/jproc.2004.840301 · Cited by 5,086
The PARSEC benchmark suite: characterization and architectural implications
Bienia, C., Kumar, S., Singh, J. P., & Li, K. (2008) · Proceedings of the 17th international conference on Parallel architectures and compilation techniques · doi:10.1145/1454115.1454128 · Cited by 3,444
Cited by
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Song, L., Qian, X., Li, H., & Chen, Y. (2017) · 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2017.55 · Cited by 833
Metadata
- Authors
- Akin, B., Franchetti, F., & Hoe, J. C.
- Venue
- Proceedings of the 42nd Annual International Symposium on Computer Architecture
- Publisher
- ACM
- Published
- 2015-06-13
- Pages
- 131-143
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W2078141470
- Cited by
- 158
- References
- 2
- FWCI
- 16.24
- Type
- conference paper
- Language
- en
- Open access
- closed
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- The paper
- Akin, B., Franchetti, F., & Hoe, J. C. (2015). Data reorganization in memory using 3D-stacked DRAM. Proceedings of the 42nd Annual International Symposium on Computer Architecture. https://doi.org/10.1145/2749469.2750397
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