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Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories
Abstract
Processing-in-memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die-stacking technology, we propose to leverage the unique features of emerging non-volatile memory (NVM), such as resistance-based storage and current sensing, to enable efficient PIM design in NVM. We propose Pinatubo1, a Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations. Instead of integrating complex logic inside the cost-sensitive memory, Pinatubo redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one-step multi-row operations. The experimental results on data intensive graph processing and database applications show that Pinatubo achieves a ~500× speedup, ~28000× energy saving on bitwise operations, and 1.12× overall speedup, 1.11× overall energy saving over the conventional processor.
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Cited by
Memory devices and applications for in-memory computing
Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R., & Eleftheriou, E. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0655-z · Cited by 2,289
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
Agrawal, A., Jaiswal, A., Lee, C., & Roy, K. (2018) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2018.2848999 · Cited by 325
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
Chen, W.-H., Dou, C., Li, K.-X., Lin, W.-Y., Li, P.-Y., Huang, J.-H., Wang, J.-H., Wei, W.-C., Xue, C.-X., Chiu, Y.-C., et al. (2019) · Nature Electronics · doi:10.1038/s41928-019-0288-0 · Cited by 276
Computing in memory with FeFETs
Reis, D., Niemier, M., & Hu, X. S. (2018) · Proceedings of the International Symposium on Low Power Electronics and Design · doi:10.1145/3218603.3218640 · Cited by 102
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training
Imani, M., Yin, X., Messerly, J., Gupta, S., Niemier, M., Hu, X. S., & Rosing, T. (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2952544 · Cited by 87
Metadata
- Authors
- Li, S., Xu, C., Zou, Q., Zhao, J., Lu, Y., & Xie, Y.
- Venue
- Proceedings of the 53rd Annual Design Automation Conference
- Publisher
- ACM
- Published
- 2016-06-05
- Pages
- 1-6
- ISSN
- 0738-100X (ISSN-L)
- OpenAlex
- W2396622873
- Cited by
- 436
- References
- 0
- FWCI
- 69.25
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Li, S., Xu, C., Zou, Q., Zhao, J., Lu, Y., & Xie, Y. (2016). Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. Proceedings of the 53rd Annual Design Automation Conference. https://doi.org/10.1145/2897937.2898064
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