The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
Abstract
Recently, FPGA-based CNN accelerators have demonstrated superior energy efficiency compared to high-performance devices like GPGPUs. However, due to the constrained on-chip resource and many other factors, single-board FPGA designs may have difficulties in achieving optimal energy efficiency. In this paper we present a deeply pipelined multi-FPGA architecture that expands the design space for optimal performance and energy efficiency. A dynamic programming algorithm is proposed to map the CNN computing layers efficiently to different FPGA boards. To demonstrate the potential of the architecture, we built a prototype system with seven FPGA boards connected with high-speed serial links. The experimental results on AlexNet and VGG-16 show that the prototype can achieve up to 21x and 2x energy efficiency compared to optimized multi-core CPU and GPU implementations, respectively.
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ImageNet classification with deep convolutional neural networks
Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155
A dynamically configurable coprocessor for convolutional neural networks
Chakradhar, S., Sankaradas, M., Jakkula, V., & Cadambi, S. (2010) · Proceedings of the 37th annual international symposium on Computer architecture · doi:10.1145/1815961.1815993 · Cited by 343
Cited by
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Li, Z., Liu, F., Yang, W., Peng, S., & Zhou, J. (2022) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2021.3084827 · Cited by 5,273
Artificial intelligence applications in the development of autonomous vehicles: a survey
Ma, Y., Wang, Z., Yang, H., & Yang, L. (2020) · IEEE/CAA Journal of Automatica Sinica · doi:10.1109/jas.2020.1003021 · Cited by 639
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020) · Neural Computing and Applications · doi:10.1007/s00521-018-3761-1 · Cited by 429
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
Ma, Y., Cao, Y., Vrudhula, S., & Seo, J.-S. (2017) · Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/3020078.3021736 · Cited by 389
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
Guo, K., Zeng, S., Yu, J., Wang, Y., & Yang, H. (2019) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3289185 · Cited by 292
Metadata
- Authors
- Zhang, C., Wu, D., Sun, J., Sun, G., Luo, G., & Cong, J.
- Venue
- Proceedings of the 2016 International Symposium on Low Power Electronics and Design
- Publisher
- ACM
- Published
- 2016-08-08
- Pages
- 326-331
- OpenAlex
- W2475840367
- Cited by
- 227
- References
- 2
- FWCI
- 21.59
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Zhang, C., Wu, D., Sun, J., Sun, G., Luo, G., & Cong, J. (2016). Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. Proceedings of the 2016 International Symposium on Low Power Electronics and Design. https://doi.org/10.1145/2934583.2934644
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