The DOI matches its Crossref record; 16 of the 16 references it cites were found in a registry or an index.
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
Abstract
As convolution layers contribute most operations in convolutional neural network (CNN) algorithms, an effective convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN accelerator. Convolution in CNNs involves three-dimensional multiply and accumulate (MAC) operations with four levels of loops, which results in a large design space. Prior works either employ limited loop optimization techniques, e.g. loop unrolling, tiling and interchange, or only tune some of the design variables after the accelerator architecture and dataflow are already fixed. Without fully studying the convolution loop optimization before the hardware design phase, the resulting accelerator can hardly exploit the data reuse and manage data movement efficiently. This work overcomes these barriers by quantitatively analyzing and optimizing the design objectives (e.g. required memory access) of the CNN accelerator based on multiple design variables. We systematically explore the trade-offs of hardware cost by searching the design variable configurations, and propose a specific dataflow of hardware CNN acceleration to minimize the memory access and data movement while maximizing the resource utilization to achieve high performance. The proposed CNN acceleration scheme and architecture are demonstrated on a standalone Altera Arria 10 GX 1150 FPGA by implementing end-to-end VGG-16 CNN model and achieved 645.25 GOPS of throughput and 47.97 ms of latency, which is a >3.2× enhancement compared to state-of-the-art FPGA implementations of VGG model.
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Cites
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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
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Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
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Cited by
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020) · Neural Computing and Applications · doi:10.1007/s00521-018-3761-1 · Cited by 429
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
Wei, X., Yu, C. H., Zhang, P., Chen, Y., Wang, Y., Hu, H., Liang, Y., & Cong, J. (2017) · Proceedings of the 54th Annual Design Automation Conference 2017 · doi:10.1145/3061639.3062207 · Cited by 426
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
Guo, K., Zeng, S., Yu, J., Wang, Y., & Yang, H. (2019) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3289185 · Cited by 292
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
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Jeon, K., Ryu, J. J., Im, S., Seo, H. K., Eom, T., Ju, H., Yang, M. K., Jeong, D. S., & Kim, G. H. (2024) · Nature Communications · doi:10.1038/s41467-023-44620-1 · Cited by 108
Metadata
- Authors
- Ma, Y., Cao, Y., Vrudhula, S., & Seo, J.-S.
- Venue
- Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
- Publisher
- ACM
- Published
- 2017-02-22
- Pages
- 45-54
- OpenAlex
- W2584311934
- Cited by
- 389
- References
- 16
- FWCI
- 37.87
- Type
- conference paper
- Language
- en
- Open access
- closed
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