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Superneurons: dynamic GPU memory management for training deep neural networks
Open accessAbstract
Going deeper and wider in neural architectures improves their accuracy, while the limited GPU DRAM places an undesired restriction on the network design domain. Deep Learning (DL) practitioners either need to change to less desired network architectures, or nontrivially dissect a network across multiGPUs. These distract DL practitioners from concentrating on their original machine learning tasks. We present SuperNeurons: a dynamic GPU memory scheduling runtime to enable the network training far beyond the GPU DRAM capacity. SuperNeurons features 3 memory optimizations, Liveness Analysis, Unified Tensor Pool, and Cost-Aware Recomputation; together they effectively reduce the network-wide peak memory usage down to the maximal memory usage among layers. We also address the performance issues in these memory-saving techniques. Given the limited GPU DRAM, SuperNeurons not only provisions the necessary memory for the training, but also dynamically allocates the memory for convolution workspaces to achieve the high performance. Evaluations against Caffe, Torch, MXNet and TensorFlow have demonstrated that SuperNeurons trains at least 3.2432 deeper network than current ones with the leading performance. Particularly, SuperNeurons can train ResNet2500 that has 104 basic network layers on a 12GB K40c.
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Zhu, Z., Giannoula, C., Andoorveedu, M., Su, Q., Mangalam, K., Zheng, B., & Pekhimenko, G. G. (2025) · European Conference on Computer Systems · doi:10.1145/3689031.3717461 · Cited by 17
Adaptive Sparse Deep Neural Network Inference on Resource-Constrained Cost-Efficient GPUs
Dun, M., Zhang, X., Cao, H., Zhang, Y., Huang, J., & Ye, X. (2023) · IEEE High Performance Extreme Computing Conference · doi:10.1109/hpec58863.2023.10363545 · Cited by 8
Profiling based out-of-core Hybrid method for large neural networks
Ito, Y., Imai, H., Duc, T. L., Negishi, Y., Kawachiya, K., Matsumiya, R., & Endo, T. (2019) · ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming · doi:10.1145/3293883.3298790 · Cited by 8
Xie, X., Liang, Y. E., Li, X., & Tan, W. (2019) · ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) · doi:10.1145/3307681.3325407 · Cited by 8
Resource scheduling techniques in cloud from a view of coordination: a holistic survey
Wang, Y., Yu, J., & Yu, Z. (2023) · Frontiers of Information Technology & Electronic Engineering · doi:10.1631/fitee.2100298 · Cited by 8
Zhao, K., Chang, Y., Wu, W., Luo, H., Li, Z., He, S., & Guo, D. (2023) · Journal of Real-Time Image Processing · doi:10.1007/s11554-023-01375-8 · Cited by 8
Self-citationThe Case for Storage Optimization Decoupling in Deep Learning Frameworks
Macedo, R., Correia, C., Dantas, M., Brito, C. V., Xu, W., Tanimura, Y., Haga, J., & Paulo, J. (2021) · IEEE International Conference on Cluster Computing (CLUSTER) · doi:10.1109/cluster48925.2021.00096 · Cited by 8
SUV: Static Analysis Guided Unified Virtual Memory
Pratheek, B., Cox, G., Veselý, J., & Basu, A. (2024) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro61859.2024.00030 · Cited by 7
Sun, Z., Chen, S.-Q., Wang, Y., Sha, J., Feng, G.-Y., & Chen, W.-G. (2025) · European Conference on Computer Systems · doi:10.1145/3689031.3717469 · Cited by 14
VGA: Hardware Accelerator for Scalable Long Sequence Model Inference
Lee, S.-Y., Lee, H.-S., Hong, J., Cho, S., & Lee, J. W. (2024) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro61859.2024.00106 · Cited by 7
Exploring Means to Enhance the Efficiency of GPU Bitmap Index Query Processing
Tran, B., Schaffner, B., Myre, J. M., Sawin, J., & Chiu, D. (2020) · Data Science and Engineering · doi:10.1007/s41019-020-00148-8 · Cited by 7
Zhang, X., Xia, H., Zhuang, D., Sun, H., Fu, X., Taylor, M. B., & Song, S. L. (2021) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca52012.2021.00051 · Cited by 7
Self-citation
Metadata
- Authors
- Wang, L., Ye, J., Zhao, Y., Wu, W., Li, A., Song, S. L., Xu, Z., & Kraska, T.
- Affiliations
- Brown University (US)
- University of Electronic Science and Technology of China (CN)
- Los Alamos National Laboratory (US)
- Pacific Northwest National Laboratory (US)
- Venue
- Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
- Publisher
- ACM
- Published
- 2018-02-10
- Pages
- 41-53
- OpenAlex
- W4301361180
- Cited by
- 175
- References
- 28
- Citations by year
- 2026: 6 · 2025: 14 · 2024: 31 · 2023: 26 · 2022: 27 · 2021: 25 · 2020: 23 · 2019: 20 · 2018: 3
- FWCI
- 15.26
- Type
- conference paper
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (publishedVersion)
- Funders
- VMware
- Mellanox
- Oracle
- Natural Science Foundation of China (61572111)
- DARPA (16-43-D3M-FP-040)
- Central Universities of China (ZYGX2016Z003)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Information Systems › Cloud Computing and Resource Management
- Keywords
- GPU memory management, deep neural network training, memory optimization, liveness analysis, dynamic memory allocation, multi-GPU training
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