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Power-constrained CMOS scaling limits
Abstract
The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of power-dissipation constraints. The primary problem is static power dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations. The details of these effects, along with other scaling issues, are discussed in the context of their dependence on application. On the basis of these considerations, the limits of CMOS scaling are estimated for various application scenarios.
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Citations
Cited by
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Digital Information Processing in Molecular Systems
Szaciłowski, K. (2008) · Chemical Reviews · doi:10.1021/cr068403q · Cited by 827
Large-scale deep unsupervised learning using graphics processors
Raina, R., Madhavan, A., & Ng, A. Y. (2009) · Proceedings of the 26th Annual International Conference on Machine Learning · doi:10.1145/1553374.1553486 · Cited by 742
Vertical Tunnel Field-Effect Transistor
Bhuwalka, K. K., Sedlmaier, S., Ludsteck, A. K., Tolksdorf, C., Schulze, J., & Eisele, I. (2004) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2003.821575 · Cited by 273
Palumbo, F., Wen, C., Lombardo, S., Pazos, S., Aguirre, F., Eizenberg, M., Hui, F., & Lanza, M. (2020) · Advanced Functional Materials · doi:10.1002/adfm.201900657 · Cited by 268
Metadata
- Authors
- Frank, D. J.
- Venue
- IBM Journal of Research and Development
- Publisher
- IBM
- Published
- 2002-03
- Volume
- 46
- Issue
- 2.3
- Pages
- 235-244
- ISSN
- 0018-8646 (ISSN-L)
- OpenAlex
- W1975112218
- Cited by
- 231
- References
- 0
- FWCI
- 10.87
- Type
- journal article
- Language
- en
- Open access
- closed
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