Cited by 22Low-power high-performance VLSI designAdvanced Memory and Neural ComputingAdvanced Neural Network Applications

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Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance

Buschjager, Sebastian, Chen, Jian-Jia, Chen, Kuan-Hsun, Gunzel, Mario, Hakert, Christian, Morik, Katharina, Novkin, Rodion, Pfahler, Lukas, Yayla, Mikail·2021·2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Abstract

To overcome the memory wall in neural network (NN) inference systems, recent studies have proposed to use approximate memory, in which the supply voltage and access latency parameters are tuned, for lower energy consumption and faster access at the cost of reliability. To tolerate the occuring bit errors, the state-of-the-art approaches apply bit flip injections to the NNs during training, which require high overheads and do not scale well for large NNs and high bit error rates. In this work, we focus on binarized NNs (BNNs), whose simpler structure allows better exploration of bit error tolerance metrics based on margins. We provide formal proofs to quantify the maximum number of bit flips that can be tolerated. With the proposed margin-based metrics and the well-known hinge loss for maximum margin classification in support vector machines (SVMs), we are able to construct a modified hinge loss (MHL) to train BNNs for bit error tolerance without any bit flip injections. Our experimental results indicate that the MHL enables the possibility for BNNs to tolerate higher bit error rates than with bit flip training and, therefore, allows to further lower the requirements on approximate memories used for BNNs.

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Crossref · 10.23919/date51398.2021.9473918

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Research works printed but not linked: 19

  1. 10.1145/3007787.3001165 · DOI · Paper page
  2. 10.1162/089976604773135104 · DOI
  3. sari, 2019, How does batch normalization help binary training?
  4. 10.1109/72.963771 · DOI
  5. 10.1109/TVLSI.2016.2644279 · DOI
  6. 10.1109/TVLSI.2017.2727528 · DOI
  7. 10.1109/ACCESS.2017.2742698 · DOI
  8. 10.1109/ISCAS.2018.8351255 · DOI
  9. yang, 0, Sram voltage scaling for energy-efficient convolutional neural networks, Quality Electronic Design (IS QED) 2017 18th International Symposium on, 7
  10. 10.1145/1015330.1015332 · DOI
  11. henwood, 2019, Layerwise noise maximisation to train low-energy deep neural networks
  12. 10.1109/ICNN.1997.616152 · DOI
  13. 10.1109/NANOARCH47378.2019.181300 · DOI
  14. 10.1109/AICAS.2019.8771544 · DOI · Paper page
  15. 10.1145/3352460.3358280 · DOI
  16. hubara, 2016, Bi-narized neural networks, Advances in neural information processing systems, 4107
  17. 10.1016/S0893-6080(98)00094-X · DOI
  18. buschjäger, 2020, Towards explainable bit error tolerance of resistive ram-based binarized neural networks, CoRR abs/2002 00909
  19. 10.1109/ICCAD45719.2019.8942068 · DOI

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Metadata

Authors
Buschjager, S., Chen, J.-J., Chen, K.-H., Gunzel, M., Hakert, C., Morik, K., Novkin, R., Pfahler, L., & Yayla, M.
Affiliations
TU Dortmund University (DE)
Venue
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Publisher
IEEE
Published
2021-02-01
Pages
673-678
OpenAlex
W3185026020
Cited by
22
References
0
Citations by year
2026: 1 · 2025: 2 · 2024: 5 · 2023: 6 · 2022: 5 · 2021: 3
FWCI
7.46
Type
conference paper
Language
en
Open access
closed
Locations
Design, Automation, and Test in Europe (publishedVersion)
Funders
Deutsche Forschungsgemeinshaft (DFG) (124020371)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
Keywords
binary neural networks, margin maximization, memory wall, neural network inference, energy efficiency

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