Deiss, Stephen

A compute-in-memory chip based on resistive random-access memory

Wan, W., Kubendran, R., Schaefer, C., Eryilmaz, S. B., Zhang, W., Wu, D., Deiss, S., Raina, P., Qian, H., Gao, B., et al. (2022) · Nature

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 943

Memory-Efficient Synaptic Connectivity for Spike-Timing- Dependent Plasticity

Pedroni, B. U., Joshi, S., Deiss, S. R., Sheik, S., Detorakis, G., Paul, S., Augustine, C., Neftci, E. O., & Cauwenberghs, G. (2019) · Frontiers in Neuroscience

Advanced Memory and Neural ComputingNeural dynamics and brain function

Cited by 29

Hierarchical Multicast Network-On-Chip for Scalable Reconfigurable Neuromorphic Systems

Hota, G., Mysore, N., Deiss, S., Pedroni, B., & Cauwenberghs, G. (2022) · 2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Interconnection Networks and SystemsAdvanced Memory and Neural Computing

Cited by 7

Hierarchical Network Connectivity and Partitioning for Reconfigurable Large-Scale Neuromorphic Systems

Mysore, N., Hota, G., Deiss, S. R., Pedroni, B. U., & Cauwenberghs, G. (2022) · Frontiers in Neuroscience

Advanced Memory and Neural ComputingVLSI and FPGA Design Techniques

Cited by 7

HiAER-spike software-hardware reconfigurable platform for event-driven neuromorphic computing at scale

Frank, G., Hota, G., Wang, K., Deng, C., Arora, K., Vins, D., Uppal, A., Olajide, O., Yoshimoto, K., Wang, Q., et al. (2026) · npj Unconventional Computing

Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques

Cited by 0