Suresh, Vikram

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Satpathy, S. K., Mathew, S. K., Kumar, R., Suresh, V., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S., Krishnamurthy, R. K., & De, V. (2019) · IEEE Journal of Solid-State Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 114

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Mathew, S. K., Johnston, D., Satpathy, S., Suresh, V., Newman, P., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S. K., Chen, G., et al. (2016) · IEEE Journal of Solid-State Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 102

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing

Suresh, V. B., & Burleson, W. P. (2015) · IEEE Transactions on Circuits and Systems I: Regular Papers

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 50