An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS
Abstract
This paper describes a unified static/dynamic entropy generator based on a 512-b common entropy source (ES) array fabricated in 14-nm tri-gate CMOS with reconfigurable and adaptive post-processing circuits implemented on Arria 10 FPGA, targeted for flexible and secure privacy preserving mutual authentication on compact trusted mote platforms at the edge of internet of things. Several conditioning techniques that include temporal majority voting (TMV)-assisted ES array segregation with integrated bias tracking, three-way in-line self-calibration for tolerance to process–voltage–temperature variation, tri-level hierarchical Von Neumann (VN) extraction to maximize entropy harvesting, soft-dark bit masking for improving physically unclonable function (PUF) stability, and selective stress hardening to co-optimize the ES array for static-dynamic entropy with bias aware device aging enable simultaneous PUF and true random number generator (TRNG) operation with 1.48 and 0.56 Gb/s throughput, respectively, measured at 650 mV, 70 °C. The all-digital design with a compact layout footprint of 2114$\mu \text{m}^{2}$facilitates seamless integration in area constrained system-on-chips while achieving: 1) 25% area savings over conventional separate PUF and TRNG implementations; 2) cryptographic quality TRNG stream that passes all NIST randomness tests with 0.38 average p-value; 3)$1.6\times $higher extractor performance at$9\times $lower area with 750-gate hierarchical VN circuit over conventional light-weight entropy extractors; 4) 0.9996/0.99997 static/dynamic Shannon entropy indicating unbiased PUF/TRNG streams; 5) ultra-low energy consumption of 2.5 and 0.46 pJ/bit measured at 650 mV, 70 °C in TRNG and PUF modes; 6) 40% higher TRNG throughput with three-way self-calibration featuring coarse-grain column swap, fine-grain incremental ES substitution, and residual entropy recycling; 7) resistance to power injection attacks as measured by 64% higher performance over un-calibrated design in the presence 200-mV supply noise; 8) 2.8% PUF bit-error measured at 0.55–0.75 V, 25 °C–110 °C with 15-way TMV and soft dark-bit masking over a window of 100 cycles; 9)$14.8\times $inter and intra-PUF hamming distance separation; and 10) 56% reduction in discarded ES cells with selective stress hardening to opportunistically reinforce/nullify pre-existing bias in PUF/TRNG candidate cells. To our knowledge, this is the first reported unified PUF-TRNG implementation enabling simultaneous generation of high-entropy chip-ID and encryption keys in real time.
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Those entropy sources rely on operation-induced variations.
“Note that those entropy sources rely on operation-induced variations (19–23).”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [22]
Si-CMOS-based tRNGs use circuitry with various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages, for low power consumption.
“In contrast, Si-CMOS–based tRNGs use circuitry that uses various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages for low power consumption.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [22]
Si-CMOS-based tRNGs show excellent randomness and insensitivity to fabrication-induced variability.
“They show excellent randomness and insensitivity to fabrication-induced variability.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [22]
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Zhang, R., Wang, X., & Shinohara, H. (2021) · IEICE Transactions on Electronics · doi:10.1587/transele.2020cdp0006 · Cited by 10 · see citing works
Japa, A., Majumder, M. K., Sahoo, S. K., & Vaddi, R. (2021) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.3030 · Cited by 10 · see citing works
Ngo, C. T., Ko, H. W., Choi, J., Nam, J.-W., & Hong, J.-P. (2024) · Sensors · doi:10.3390/s24237502 · Cited by 9 · see citing works
Correlation free large-scale probabilistic computing using a true-random chaotic oscillator p-bit
Lee, W., Kim, H., Jung, H., Choi, Y., Jeon, J., & Kim, C. (2025) · Scientific Reports · doi:10.1038/s41598-025-93218-8 · Cited by 9 · see citing works
A Unified Approach to Strong PUF and TRNG Using Ring Generator for Cryptography
Dang, T.-K., Nguyen, K.-D., Hoang, T.-T., & Pham, C. (2025) · IEEE Internet of Things Journal · doi:10.1109/jiot.2025.3582869 · Cited by 9 · see citing works
Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach
Kumar, D., Kesarwani, H., Kandpal, K., Misra, P. K., & Goswami, M. (2021) · International Conference on Signal Processing and Integrated Networks (SPIN) · doi:10.1109/spin52536.2021.9566149 · Cited by 8 · see citing works
Wang, X., Zhang, R., Liu, K., & Shinohara, H. (2023) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2023.3328602 · Cited by 8 · see citing works
A design of cellular automata‐based PUF and its implementation on FPGA
Göncü, E., & Yalcin, M. E. (2020) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.2792 · Cited by 8 · see citing works
A Compact and Power-Efficient Noise Generator for Stochastic Simulations
Zhao, H., Sarpeshkar, R., & Mandal, S. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3199561 · Cited by 8 · see citing works
Weak Physically Unclonable Functions in CMOS Technology: A Review
Vatalaro, M., Rose, R. D., Lanuzza, M., & Crupi, F. (2024) · Chips · doi:10.3390/chips4010003 · Cited by 7 · see citing works
Zhang, Y., Zhong, K., & Zhang, J. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3572838 · Cited by 7 · see citing works
Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure
Zhang, X., Jiang, C., Dai, G., Zhong, L., Fang, W., Gu, K., Xiao, G., Ren, S., Liu, X., & Zou, S. (2020) · Sensors · doi:10.3390/s20216132 · Cited by 7 · see citing works
Bifurcation Generated True Random Numbers In Nonlinear Micromechanical Resonators
Chen, T.-Y., & Li, W. (2024) · IEEE International Conference on Micro Electro Mechanical Systems (MEMS) · doi:10.1109/mems58180.2024.10439431 · Cited by 7 · see citing works
A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator
Kumar, D., Mankali, L. L., Misra, P. K., & Goswami, M. (2020) · IETE Journal of Research · doi:10.1080/03772063.2020.1859957 · Cited by 7 · see citing works
Predictor-corrector models for lightweight massive machine-type communications in Industry 4.0
Bordel, B., Alcarria, R., Chung, J., & Kettimuthu, R. (2023) · Integrated Computer-Aided Engineering · doi:10.3233/ica-230713 · Cited by 6 · see citing works
A 10-Gbps, 0.121-pJ/bit, All-Digital True Random-Number Generator using Middle Square Method
Kim, J., & Chae, H. (2022) · IEEE Asian Solid-State Circuits Conference (A-SSCC) · doi:10.1109/a-sscc56115.2022.9980831 · Cited by 6 · see citing works
Li, X., Wang, Y., Yi-ming, Y., Lv, S., Luo, Q., Wang, X., Xu, X., Lei, D., & Zhang, F. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3288839 · Cited by 6 · see citing works
A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF
Shifman, Y., Miller, A., Keren, O., Weizman, Y., & Shor, J. S. (2020) · IEEE Access · doi:10.1109/access.2020.3042092 · Cited by 6 · see citing works
33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator
Chandrasekaran, S. T., Jayaraj, A., Ramesh, N., & Sanyal, A. (2021) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas51556.2021.9401507 · Cited by 5 · see citing works
Kumar, D., Anand, R., Singh, S. V., Misra, P. K., Srivastava, A. K., & Goswami, M. (2020) · IET Circuits Devices & Systems · doi:10.1049/iet-cds.2019.0318 · Cited by 5 · see citing works
Taneja, S., & Alioto, M. (2020) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2020.3025191 · Cited by 5 · see citing works
Wang, X., Zhang, R., Wang, Y., Liu, K., Wang, X., & Shinohara, H. (2022) · International Symposium on VLSI Design, Automation and Test · doi:10.1109/vlsi-dat54769.2022.9768078 · Cited by 5 · see citing works
Lee, J. W., Han, J., Kim, S., Maeng, H.-Y., Yun, S., Son, J.-H., Lee, S.-W., & Choi, Y. (2024) · Nano Research · doi:10.26599/nr.2025.94907045 · Cited by 4 · see citing works
24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS
Chen, C.-B., Chen, T., & Huang, Y.-H. (2025) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2025.3605369 · Cited by 4 · see citing works
Elmitwalli, E., Ni, K., & Köse, S. (2021) · IEEE Access · doi:10.1109/access.2021.3120047 · Cited by 4 · see citing works
Mirror N PUF: Harvesting Multiple Independent Bits From Each PUF Cell in 65nm
Shifman, Y., Fish, A., & Shor, J. S. (2022) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas48785.2022.9937229 · Cited by 4 · see citing works
True random number generators in modern cryptography: A review
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A true random number generator with high bit rate and low energy efficiency
Cheng, X., Zhang, Y., Zhu, H., & Zhou, Y. (2023) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.3563 · Cited by 3 · see citing works
A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications
Pan, Z., Cheng, J., Sun, N., Wang, J., Shi, K., Li, J., Niu, Z., Wang, J., Zhang, J., Wang, L., et al. (2025) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2025.105170 · Cited by 2 · see citing works
AuthentiSafe: Lightweight and Future-Proof Device-to-Device Authentication for IoT
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Cheng, K. M., Chen, Y., Crovetti, P., Martins, R. P., & Mak, P. (2024) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.4065 · Cited by 2 · see citing works
Lee, W., Sim, C., Kim, C., Jeon, J.-W., Jung, H., Kim, T., & Kim, C. (2025) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2025.3608187 · Cited by 1 · see citing works
Wang, T., Basu, J., Rajanna, V. K., & Alioto, M. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3608858 · Cited by 1 · see citing works
Kim, S.-I., Chin, H.-S., Han, J.-A., Kim, S., Kim, J., Lee, S., Lee, D. H., Kim, M., Ryu, S., & Choi, Y. (2025) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.5c18669 · Cited by 1 · see citing works
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability-Enhanced Entropy with 2.2 Gbps Throughput
Zhang, Y., & Zhang, J. (2025) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3779443 · Cited by 1 · see citing works
Circuits for Secure Root-of-Trust: TRNG, PUF, Attack-Resistant Cryptographic Accelerators [Feature]
Mathew, S. K., Kumar, R., & De, V. K. (2025) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2025.3595508 · Cited by 1 · see citing works
Self-citationCheng, K., Huang, Y., Yang, Z., Wang, L., Ren, H., Shan, X., Mak, P., Chen, Y., & Li, B. (2026) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc49663.2026.11409134 · Cited by 1 · see citing works
Unified PUF and TRNG Design Using SOT-MTJ Crossbar Array
Das, K. K., Nisar, A., Kaushik, B. K., Chattopadhyay, A., & Zahoor, F. (2025) · IEEE Transactions on Magnetics · doi:10.1109/tmag.2025.3574994 · Cited by 1 · see citing works
Design and Synthesis of Random Number Generator Using LFSR
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A Unified TRNG And PUF Module Based on Threshold Switching Array
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Self-Destructible 3-nm Pre-Amplifier Physical Unclonable Function With “Zero” Bit Error Rate
Hunt-Schroeder, E., Degada, A., & Xia, T. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3593193 · Cited by 1 · see citing works
Designing, Implementing, and Testing Hardware for Cybersecurity
Brown, J. (2021) · Liverpool John Moores University · doi:10.24377/ljmu.t.00014649 · Cited by 1 · see citing works
2019 Index IEEE Journal of Solid-State Circuits Vol. 54
(2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2956675
Kumar, D., Chaurasia, U. K., Mishra, S., Patel, P. S., Misra, P. K., & Goswami, M. (2021) · Journal of Circuits Systems and Computers · doi:10.1142/s0218126621502856
Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation
Sridevi, G. M., Ashoka, D. V., & Vijaya, A. P. B. (2022) · Karbala International Journal of Modern Science · doi:10.33640/2405-609x.3223
(2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2905124
Anusha, B., & Manindar, M. A. (2022) · Algorithms for intelligent systems · doi:10.1007/978-981-19-1669-4_33
Wang, X., Zhang, R., & Shinohara, H. (2023) · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · doi:10.1587/transfun.2023kep0011
5G-SRNG: 5G Spectrogram-based Random Number Generation for Devices with Low Entropy Sources
Çatak, F. Ö., Çatak, E., & Elezaj, O. (2023) · IEEE International Conference on Omni-layer Intelligent Systems (COINS) · doi:10.1109/coins57856.2023.10189262
Feedback reinforced accelerated aging for improved physical unclonable function stability
Hunt-Schroeder, E., & Xia, T. (2025) · Microelectronics Reliability · doi:10.1016/j.microrel.2025.115592
Metastability-based random number generator with current-controlled offset compensation
Talay, Y. (2025) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-024-02298-5
A Unified Oscillator-Based TRNG and PUF with a Gate-Tunneling Entropy Source
Douthwaite, M., Varici, A., & Desikachari, R. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043650
Kim, J., & Chen, V. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3602728
Zhang, R., Cao, Y., Zhang, H., Cheng, Q., Nishizawa, S., Niitsu, K., & Shinohara, H. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3621604
- Authors
- Satpathy, S. K., Mathew, S. K., Kumar, R., Suresh, V., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S., Krishnamurthy, R. K., & De, V.
- Affiliations
- Intel (United States) (US)
- ORCID
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2019-04
- Volume
- 54
- Issue
- 4
- Pages
- 1074-1085
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2908207594
- Cited by
- 114
- References
- 48
- Citations by year
- 2026: 15 · 2025: 21 · 2024: 13 · 2023: 14 · 2022: 16 · 2021: 15 · 2020: 17 · 2019: 3
- FWCI
- 12.98
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Keywords
- physical unclonable functions, true random number generator, entropy source, self-calibration, device aging, PVT variation, mutual authentication, Internet of Things security, low-power electronics
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