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Tolerating Noise Effects in Processing‐in‐Memory Systems for Neural Networks: A Hardware–Software Codesign Perspective
Open accessAbstract
Neural networks have been widely used for advanced tasks from image recognition to natural language processing. Many recent works focus on improving the efficiency of executing neural networks in diverse applications. Researchers have advocated processing‐in‐memory (PIM) architecture as a promising candidate for training and testing neural networks because PIM design can reduce the communication cost between storage and computing units. However, there exist noises in the PIM system generated from the intrinsic physical properties of both memory devices and the peripheral circuits. The noises introduce challenges in stably training the systems and achieving high test performance, e.g., accuracy in classification tasks. This review discusses the current approaches to tolerating noise effects for both training and inference in PIM systems and provides an analysis from a hardware–software codesign perspective. Noise‐tolerant strategies for PIM systems based on resistive random‐access memory (ReRAM), including circuit‐level, algorithm‐level, and system‐level solutions are explained. In addition, we also present some selected noise‐tolerate cases in PIM systems for generative adversarial networks and physical neural networks.
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Noise-aware training-simple injection of noise onto weights or activations during DNN training-can make DNNs more robust for AIMC deployment.
“A number of previous studies have shown that noise-aware training —simple injection of noise onto weights or activations during DNN training—can make DNNs more robust for AIMC deployment33,38–42.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [39]
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Sorted by citations
Rasch, M. J., Mackin, C., Le Gallo, M., Chen, A., Fasoli, A., Odermatt, F., Li, N., Nandakumar, S. R., Narayanan, P., Tsai, H., et al. (2023) · Nature Communications · doi:10.1038/s41467-023-40770-4 · Cited by 213
“Thus more realistic and standardized AIMC crossbar models — which can support comparison of AIMC accuracy for hardware-aware trained DNN models across studies — are needed.”
Method
Metadata
- Authors
- Yang, X., Wu, C., Li, M., & Chen, Y.
- Affiliations
- Duke University (US)
- University of Washington (US)
- Corresponding author
- Yang, Xiaoxuan
- Chen, Yiran
- Venue
- Advanced Intelligent Systems
- Publisher
- Wiley
- Published
- 2022-05-22
- Volume
- 4
- Issue
- 8
- ISSN
- 2640-4567 (ISSN-L)
- OpenAlex
- W4281289797
- Cited by
- 22
- References
- 3
- Citations by year
- 2026: 4 · 2025: 5 · 2024: 3 · 2023: 8 · 2022: 2
- FWCI
- 1.23
- Type
- journal article
- Language
- en
- Open access
- gold
- doi.org
- Locations
- Advanced Intelligent Systems (publishedVersion, cc-by)
- DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion)
- Funders
- National Science Foundation (1955196)
- Army Research Office (W911NF-19-2-0107)
- Office of Naval Research (N00014-17-1-2661)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
- Keywords
- in-memory computing, noise immunity, neural network training, neural network inference, hardware-software co-design, resistive random access memory, generative adversarial networks, physical neural networks, classification accuracy
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