A Very Compact S-Box for AES
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On Spartan-7 devices, the standard AES S-box remains more compact in terms of resource utilization than the proposed S-box in [3].
“However, on Spartan-7 devices, the standard AES S-box remains more compact in terms of resource utilization.”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
The proposed S-box in [3] achieves better area efficiency on Artix-7, Zynq, and Kintex Ultra-Scale+ platforms than the conventional AES S-box.
“The proposed S-box in [3] achieves better area efficiency on Artix-7, Zynq, and Kintex Ultra-Scale+ platforms.”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
The advantages of the compact S-box from [3] are less evident in high-resource designs like our multi-core WAES-256 implementations, where overall resource utilization is dominated by wide data paths and extensive pipelining.
“However, the advantages of this compact S-box are less evident in high-resource designs like our multi-core WAES-256 implementations, where the overall resource utilization is dominated by the wide data paths and extensive pipelining required for high throughput.”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
The design evaluated the compact S-box proposed by [3].
“Additionally, we evaluated the compact S-box proposed by [3] within our design.”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
In pipelined architecture on Kintex UltraScale+ KCU116, the proposed S-Box [3] uses 54 LUT/44 FF, compared to AES's S-Box which uses 56 LUT/44 FF.
“| Kintex UltraScale+ KCU116 56 LUT / 44 FF | 54 LUT / 44 FF | |”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
In pipelined architecture on Spartan-7 SP701, the proposed S-Box [3] uses 57 LUT/44 FF, compared to AES's S-Box which uses 53 LUT/44 FF.
“| Spartan-7 SP701 | 53 LUT / 44 FF | 57 LUT / 44 FF |”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
In pipelined architecture on Zynq UltraScale+ ZCU1006, the proposed S-Box [3] uses 54 LUT/44 FF, compared to AES's S-Box which uses 56 LUT/44 FF.
“| Zynq UltraScale+ ZCU1006 | 56 LUT / 44 FF | 54 LUT / 44 FF |”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
In pipelined architecture on Artix-7 AC701, the proposed S-Box [3] uses 57 LUT/44 FF, compared to AES's S-Box which uses 58 LUT/44 FF.
“| Artix-7 AC701 | 58 LUT / 44 FF | 57 LUT / 44 FF |”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [3]
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A Compact Rijndael Hardware Architecture with S-Box Optimization
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Very Compact FPGA Implementation of the AES Algorithm
Chodowiec, P., & Gaj, K. (2003) · Lecture notes in computer science · doi:10.1007/978-3-540-45238-6_26 · Cited by 313 · see citing works
An ASIC Implementation of the AES SBoxes
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An Optimized S-Box Circuit Architecture for Low Power AES Design
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Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
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Efficient Implementation of the Rijndael S-box
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A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
Jarvinen, K. U., Tommiska, M. T., & Skyttä, J. O. (2003) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/611817.611848 · Cited by 135 · see citing works
A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box
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Self-citationA 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
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Quantum reversible circuit of AES-128
Almazrooie, M., Samsudin, A., Abdullah, R., & Mutter, K. N. (2018) · Quantum Information Processing · doi:10.1007/s11128-018-1864-3 · Cited by 75 · see citing works
FPGA-friendly compact and efficient AES-like 8 × 8 S-box
Malal, A., & Tezcan, C. (2024) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2024.105007 · Cited by 7 · see citing works
Malal, A., & Tezcan, C. (2026) · Journal of Cryptographic Engineering · doi:10.1007/s13389-025-00388-2 · Cited by 3 · see citing works
“We used the composite field arithmetic method proposed by [3] for efficient S-box computation.”
- Authors
- Canright, D.
- Affiliations
- Naval Postgraduate School (US)
- Corresponding author
- Canright, D.
- Venue
- Lecture Notes in Computer Science
- Publisher
- Springer Berlin Heidelberg
- Published
- 2005
- Pages
- 441-455
- ISSN
- 0302-9743 (ISSN-L)
- 1611-3349
- OpenAlex
- W2149174385
- Cited by
- 530
- References
- 12
- Citations by year
- 2026: 20 · 2025: 27 · 2024: 20 · 2023: 20 · 2022: 25 · 2021: 26 · 2020: 31 · 2019: 29 · 2018: 30 · 2017: 43 · 2016: 38 · 2015: 30 · 2014: 30 · 2013: 26 · 2012: 22
- FWCI
- 10.23
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Lecture notes in computer science (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Computer Science › Information Systems › Cryptography and Residue Arithmetic
- Physical Sciences › Computer Science › Artificial Intelligence › Coding theory and cryptography
- Keywords
- AES S-box, Advanced Encryption Standard, hardware implementation, subfields, normal bases, polynomial basis, NOR gate, smart cards, area optimization
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