Cited by 27Advanced Neural Network ApplicationsEmbedded Systems Design TechniquesEmbedded Systems and FPGA Applications

Boosting Convolutional Neural Networks Performance Based on FPGA Accelerator

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Al-Shamma, Omran, Fadhel, Mohammed Abdulraheem, Hameed, Rabab Alaa, Alzubaidi, Laith, Zhang, Jinglan·2020·Advances in Intelligent Systems and Computing

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Crossref · 10.1007/978-3-030-16657-1_47

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23 of 23 references verified0 citation errors · 0 not checkable

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  • FPGA is widely utilized in various tasks including deep learning.

    “FPGA is wildly utilized in various tasks including deep learning [199, 247, 331–334].”

    From Review of deep learning: concepts, CNN architectures, challenges, applications, future directions (2021) · cites this paper as [199]

    The Abstract and Introduction describe several FPGA-based accelerators for deep CNNs, supporting FPGA use in deep learning. The paper does not establish the broader claim that FPGAs are widely used across various tasks beyond that area; the Introduction’s examples of speech and vision applications describe CNNs, not FPGA use in each application. Page numbers are unavailable in our copy. (LLM, conf=0.82)

    Experimental — accuracy not yet measured
  • Field programmable gate array technology is an emerging hardware technology developed in recent years.

    “Field programmable gate array (FPGA) technology is an emerging hardware technology developed in recent years [21].”

    From Face Recognition Based on Deep Learning and FPGA for Ethnicity Identification (2022) · cites this paper as [21]

    The Introduction (page not provided) describes recent developments in FPGA technology and growing use of FPGA-based CNN accelerators. It does not say that FPGA technology itself is emerging or was developed in recent years. (LLM, conf=0.82)

    Experimental — accuracy not yet measured

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Research works printed but not linked: 3

  1. Alzubaidi, L., et al. : Nucleus detection in H&E images with fully convolutional regression networks. Proc. First International Workshop on Deep Learning for Pattern Recognition. 2016.
  2. Shafiee, Ali, et al.: ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Computer Architecture News 44.3 (2016): 14- 26.
  3. Chi, Ping, et al.: Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. ACM SIGARCH Computer Architecture News. Vol. 44. No. 3. IEEE Press, 2016.

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Authors
Al-Shamma, O., Fadhel, M. A., Hameed, R. A., Alzubaidi, L., & Zhang, J.
Affiliations
  • University of Information Technology and Communications (IQ)
  • University of Baghdad (IQ)
  • Queensland University of Technology (AU)
Corresponding author
Fadhel, Mohammed Abdulraheem
Venue
Advances in Intelligent Systems and Computing
Published
2019-04-12
Pages
509-517
ISSN
  • 2194-5357 (ISSN-L)
  • 2194-5365
OpenAlex
W2946390442
Cited by
27
References
23
Citations by year
2024: 4 · 2023: 1 · 2022: 1 · 2021: 12 · 2020: 7 · 2019: 2
FWCI
1.77
Type
conference paper
Language
en
Open access
Locations
  • Advances in intelligent systems and computing (publishedVersion)
  • QUT ePrints (Queensland University of Technology) (submittedVersion)
Topics
  • Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
  • Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
Keywords
convolutional neural networks, FPGA accelerator, VGG16, hardware acceleration, fixed-point arithmetic, floating-point to fixed-point conversion, computation time reduction, image recognition, parallel computing

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