The DOI matches its Crossref record; 42 of the 42 references it cites were found in a registry or an index.
A fast and scalable architecture to run convolutional neural networks in low density FPGAs
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Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
In the citing paper
“The 8-bit mixed fixed-point representation for weights and activation are able to improve performance and reduce the loss of accuracy in hardware [22].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [22]
In the citing paper
“At the same, this architecture is able to increase the throughput by focusing on image batching at the FC layers and fixed-point arithmetic at the convolution layers.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [22]
Citations
Cites
Deep Residual Learning for Image Recognition
He, K., Zhang, X., Ren, S., & Sun, J. (2016) · 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2016.90 · Cited by 235,474
Very Deep Convolutional Networks for Large-Scale Image Recognition
Simonyan, K., & Zisserman, A. (2014) · arXiv · doi:10.48550/arxiv.1409.1556 · Cited by 114,148
ImageNet classification with deep convolutional neural networks
Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155
Going deeper with convolutions
Szegedy, C., Liu, W., Jia, Y., Sermanet, P., Reed, S., Anguelov, D., Erhan, D., Vanhoucke, V., & Rabinovich, A. (2015) · 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2015.7298594 · Cited by 48,562
ImageNet Large Scale Visual Recognition Challenge
Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al. (2015) · International Journal of Computer Vision · doi:10.1007/s11263-015-0816-y · Cited by 39,380
Han, S., Mao, H., & Dally, W. J. (2015) · arXiv · doi:10.48550/arxiv.1510.00149 · Cited by 4,662
2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)
(2015) · doi:10.1109/cvpr31182.2015 · Cited by 3,826
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158
Proceedings for the 5th International Conference on Learning Representations
Srivastava, A., & Sutton, C. A. (2017) · Cited by 1,829
DaDianNao: A Machine-Learning Supercomputer
Chen, Y., Luo, T., Liu, S., Zhang, S., He, L., Wang, J., Li, L., Chen, T., Xu, Z., Sun, N., et al. (2014) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro.2014.58 · Cited by 1,547
Cited by
Sorted by citations
Design possibilities and challenges of DNN models: a review on the perspective of end devices
Hussain, H., Tamizharasan, P. S., & Rahul, C. S. (2022) · Artificial Intelligence Review · doi:10.1007/s10462-022-10138-z · Cited by 118
Embedded Intelligence on FPGA: Survey, Applications and Challenges
Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105
“The 8-bit mixed fixed-point representation for weights and activation are able to improve performance and reduce the loss of accuracy in hardware [22].”
BackgroundMethodInfluentialA Full Featured Configurable Accelerator for Object Detection With YOLO
Pestana, D. G., Miranda, P. R., Lopes, J. D., Duarte, R. P., Véstias, M. P., Neto, H. C., & de Sousa, J. T. (2021) · IEEE Access · doi:10.1109/access.2021.3081818 · Cited by 97
Self-citationVukićević, A. M., Petrovic, M., Milošević, P., Peulić, A., Jovanovic, K. M., & Novakovic, A. (2024) · Artificial Intelligence Review · doi:10.1007/s10462-024-10978-x · Cited by 76
Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction
Wardana, I. N. K., Gardner, J. W., & Fahmy, S. A. (2021) · Sensors · doi:10.3390/s21041064 · Cited by 61
Metadata
- Authors
- Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C.
- Affiliations
- Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento (PT)
- Corresponding author
- Véstias, Mário P.
- Venue
- Microprocessors and Microsystems
- Publisher
- Elsevier BV
- Published
- 2020-09
- Volume
- 77
- Pages
- 103136
- ISSN
- 0141-9331 (ISSN-L)
- OpenAlex
- W3028015399
- Cited by
- 33
- References
- 42
- Citations by year
- 2026: 1 · 2025: 3 · 2024: 8 · 2023: 6 · 2022: 4 · 2021: 6 · 2020: 5
- FWCI
- 2.04
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- Microprocessors and Microsystems (publishedVersion)
- Portuguese National Funding Agency for Science, Research and Technology (RCAAP Project by FCT) (submittedVersion)
- Funders
- Fundação para a Ciência e a Tecnologia (UIDB/50021/2020)
- Instituto Politécnico de Lisboa (IPL/IDI&CA/2019/inCNeuralN/ISEL)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- convolutional neural networks, FPGA, CNN inference, fixed-point arithmetic, memory bandwidth reduction, embedded deep learning, scalable hardware architecture, AlexNet, Zynq-7000
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Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
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- CoChat. (2026). Citation check: A fast and scalable architecture to run convolutional neural networks in low density FPGAs. https://app.cochat.ai/papers/10.1016/j.micpro.2020.103136
- The paper
- Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2020). A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocessors and Microsystems. https://doi.org/10.1016/j.micpro.2020.103136
