SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing
Abstract
The design of neuromorphic chips aims to develop electronic circuits dedicated to executing artificial neural networks, mainly by exploring parallel processing. Unsupervised learning models, such as Self-organizing Maps (SOM), may benefit from massively concurrent hardware-based implementations to meet the requirements of real-time and embedded applications. This work first presents a theoretical analysis of the algorithms implemented in hardware to compute SOM learning and recall phases. This is important because, albeit similar, the processing steps executed in hardware are not necessarily identical to those executed in software. Then, the proposed FPGA architecture entitled SOMprocessor is shown in detail. The circuit of the processor explores two different computational strategies for increasing the performance of current state-of-the-art works. These computational strategies aim to improve the data flow through the processor and its flexibility to implement different network topologies. Finally, this work presents the application of the SOMprocessor to a video categorization task. The results show that topographic and quantization errors are similar between hardware and software implementations, as well as the overall accuracy. Moreover, the proposed FPGA architecture achieves acceleration of 3 to 4 orders of magnitude as compared to CPU executions.
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Using multiplexers allows resources to be reused for larger networks, such as reusing fixed-size blocks for computing large amounts of data and reusing the circuit for decision making and the weight update component.
“The benefit of using multiplexers is due to the ability to reuse the resources for larger networks, such as reusing the fixed size blocks for computing large amounts of data, and reusing the circuit for decision making and the weight update component [52].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [52]
The proposed FPGA architecture improves overall acceleration by three to four orders of magnitude compared to CPU execution.
“The proposed architecture will use the FPGA platform and show that it is able to improve the overall acceleration by three to four orders of magnitude as compared to CPU execution.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [52]
The proposed architecture of SOMs achieved a higher magnitude order relation than software implementation of the same order.
“As a conclusion, the proposed architecture of SOMs was able to achieve a higher magnitude order relation than software implementation of the same order.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [52]
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“The control unit is responsible for data transfer across the entire architecture [52].”
BackgroundMethodInfluentialA Survey of Hardware Self-Organizing Maps
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Dias, L. A., Damasceno, A. M. P., Gaura, E. I., & Fernandes, M. A. C. (2021) · Neural Networks · doi:10.1016/j.neunet.2021.05.021 · Cited by 18 · see citing works
Self organizing maps for cultural content delivery
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Self-organising maps for the exploration and classification of thin-layer chromatograms
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A cascade perceptron and Kohonen network approach to fault location in rural distribution feeders
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A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation
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A Data Sharing and Integration Technology for Heterogeneous Databases
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An Efficient Parallel CRC Computing Method for High Bandwidth Networks and FPGA Implementation
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Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture
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Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors
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HLS-Based Large Scale Self-Organizing Feature Maps
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SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices
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Video Chunk Processor: Low-Latency Parallel Processing of 3 x 3-pixel Image Kernels
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Hardware Self-Organizing Map With Dithered Step Neighborhood Function
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Interpretable inverse iteration mean shift networks for clustering tasks
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An Area-Efficient and Low-Error FPGA-Based Sigmoid Function Approximation
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Self-citationEdge-Cell Graph Encoding and Fixed-Point Arithmetic for FPGA Growing Neural Gas
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- Authors
- Sousa, M. A. D. A. D., Pires, R., & Del-Moral-Hernandez, E.
- Affiliations
- Federal Institute of São Paulo (BR)
- Universidade de São Paulo (BR)
- Corresponding author
- Sousa, Miguel Angelo de Abreu de
- Venue
- Neural Networks
- Publisher
- Elsevier BV
- Published
- 2020-05
- Volume
- 125
- Pages
- 349-362
- ISSN
- 0893-6080 (ISSN-L)
- OpenAlex
- W3010523544
- Cited by
- 30
- References
- 113
- Citations by year
- 2026: 1 · 2025: 3 · 2024: 3 · 2023: 5 · 2022: 5 · 2021: 8 · 2020: 5
- FWCI
- 2.26
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- Neural Networks (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Keywords
- self-organizing maps, FPGA architecture, hardware implementation of neural networks, neuromorphic hardware, video classification, topographic error, quantization error, hardware acceleration, parallel computing
- MeSH terms
- Machine Learning, Computers, Electronics, Image Processing, Computer-Assisted, Software
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