Implementation and applications of tri-state self-organizing maps on FPGA
Open accessAbstract
This paper introduces a tri-state logic self-organizing map (bSOM) designed and implemented on a field programmable gate array (FPGA) chip. The bSOM takes binary inputs and maintains tri-state weights. A novel training rule is presented. The bSOM is well suited to FPGA implementation, trains quicker than the original self-organizing map (SOM), and can be used in clustering and classification problems with binary input data. Two practical applications, character recognition and appearance-based object identification, are used to illustrate the performance of the implementation. The appearance-based object identification forms part of an end-to-end surveillance system implemented wholly on FPGA. In both applications, binary signatures extracted from the objects are processed by the bSOM. The system performance is compared with a traditional SOM with real-valued weights and a strictly binary weighted SOM.
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The traditional SOM method focuses on a binary version of SOM, using Hamming distance to identify best match units, allowing high-speed computation of the SOM learning phase by executing large SOM using moderate-density FPGAs to speed up data mining.
“The traditional SOM method is more focused on a binary version of SOM, using Hamming distance to identify the best match units (BMU) [53], allowing for the use of high speed computation of the SOM learning phase by executing large SOM using a moderate density of FPGAs to speed up the data mining operations.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [53]
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Sorted by citations
Embedded Intelligence on FPGA: Survey, Applications and Challenges
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“distance to identify the best match units (BMU) [53], allowing for the use of high speed computation of the SOM learning phase by executing large SOM using a moderate density of FPGAs to speed up the data mining operations.”
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- Authors
- Appiah, K., Hunter, A., Dickinson, P., & Meng, H.
- Affiliations
- University of Lincoln (GB)
- Brunel University of London (GB)
- Venue
- IEEE Transactions on Circuits and Systems for Video Technology
- Published
- 2012-08
- Volume
- 22
- Issue
- 8
- Pages
- 1150-1160
- ISSN
- 1051-8215 (ISSN-L)
- 1558-2205
- OpenAlex
- W1991088727
- Cited by
- 28
- References
- 32
- Citations by year
- 2026: 1 · 2023: 1 · 2022: 2 · 2021: 2 · 2020: 1 · 2019: 4 · 2018: 3 · 2017: 3 · 2015: 7 · 2014: 2 · 2013: 1 · 2012: 1
- FWCI
- 3.46
- Type
- journal article
- Language
- en
- Open access
- green
- bura.brunel.ac.uk
- Locations
- IEEE Transactions on Circuits and Systems for Video Technology (publishedVersion)
- Lincoln Repository (University of Lincoln) (acceptedVersion)
- Brunel University Research Archive (BURA) (Brunel University London) (submittedVersion)
- UCL Discovery (University College London) (submittedVersion)
- Figshare (submittedVersion, cc-by)
- Nottingham Trent University's Institutional Repository (Nottingham Trent Repository) (submittedVersion)
- SHURA (Sheffield Hallam University Research Archive) (Sheffield Hallam University) (submittedVersion)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Network Packet Processing and Optimization
- Keywords
- self-organizing maps, FPGA implementation, training rules, clustering, classification, character recognition, surveillance systems, neural network hardware
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