The DOI matches its Crossref record.
Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
In the UTB, it is hard to achieve secondary accumulation with negative VS due to stronger electric fields from the primary gate.
“Also, it is hard to achieve the secondary accumulation with the negative VS, due to stronger electric fields arisen from the primary gate21.”
From Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body (2014) · cites this paper as [21]
In the UTB, an entire body is essentially controlled by the primary gate, providing abnormal properties such as volume inversion carriers.
“In the UTB, an entire body is essentially controlled by the primary gate, providing abnormal properties, such as the volume inversion carriers2122.”
From Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body (2014) · cites this paper as [21]
The uniform and larger shifts without leakage currents in the 4.3-nm body device are attributed to the UTB imposing a much stronger interface coupling than normal capacitive-coupling.
“It is attributed to the UTB which imposes a much stronger interface coupling than the normal capacitive-coupling21.”
From Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body (2014) · cites this paper as [21]
The UTB enables the two curves of a superimposed plot of VS versus and versus the primary gate bias (VP) to coincide.
“Additionally, the UTB enables the two curves of a superimposed plot of VS versus and versus the primary gate bias (VP) to coincide2122.”
From Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body (2014) · cites this paper as [21]
Citations
Cites
No references could be resolved yet.
Research works printed but not linked: 4
- Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87.
- Celler, 2003, Frontiers of silicon-on-insulator, J Appl Phys, 93, 4955, 10.1063/1.1558223 · DOI
- Lim, 1983, Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs, IEEE Trans Electron Dev, 30, 1244, 10.1109/T-ED.1983.21282 · DOI
- Ohata, 2005, Correct biasing rules for virtual DG mode operation in SOI-MOSFETs, IEEE Trans Electron Dev, 52, 124, 10.1109/TED.2004.841273 · DOI
Cited by
Sorted by citations
Jang, H.-J., & Cho, W.-J. (2014) · Scientific Reports · doi:10.1038/srep05284 · Cited by 103
Metadata
- Authors
- Eminente, S., Cristoloveanu, S., Clerc, R., Ohata, A., & Ghibaudo, G.
- Affiliations
- Institut polytechnique de Grenoble (FR)
- Corresponding author
- Eminente, S.
- Venue
- Solid-State Electronics
- Publisher
- Elsevier BV
- Published
- 2007-02
- Volume
- 51
- Issue
- 2
- Pages
- 239-244
- ISSN
- 0038-1101 (ISSN-L)
- OpenAlex
- W2072938838
- Cited by
- 139
- References
- 0
- Citations by year
- 2026: 4 · 2025: 4 · 2024: 4 · 2023: 4 · 2022: 3 · 2021: 9 · 2020: 8 · 2019: 7 · 2018: 7 · 2017: 12 · 2016: 10 · 2015: 9 · 2014: 9 · 2013: 5 · 2012: 10
- FWCI
- 5.65
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- Solid-State Electronics (publishedVersion)
- HAL (submittedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor materials and devices
- Physical Sciences › Materials Science › Electronic, Optical and Magnetic Materials › Semiconductor materials and interfaces
- Keywords
- ultra-thin body MOSFET, fully depleted SOI, interface coupling, accumulation regime, charge properties, potential distribution, electron and hole concentration, device characterization, analytical modelling, device scaling
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
