Designing efficient accelerator of depthwise separable convolutional neural network on FPGA
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The depthwise separable CNN work showed that 16-bit fixed point multiplication consumed 6.2 times less energy than 32-bit floating point, with a small accuracy loss of 0.5%.
“Based on the research, their experimental work showed that 16-bit fixed point multiplication consumed 6.2 times less energy than the 32-bit floating point, with a small accuracy loss of 0.5%.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [24]
The depthwise separable CNN design could improve performance times by up to 17.6 times faster than CPU while using 29.4 times less energy than GPU for a 32 × 32 × 3 image size.
“The work concluded that the design could improve performance times by up to 17.6 times faster than CPU while using 29.4 times less energy than GPU for a 32 × 32 × 3 image size [24].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [24]
A depthwise separable convolution neural network on FPGA reduces the number of model parameters and improves calculation speeds, making it widely used in mobile edge computing applications.
“In the research [24], a depthwise separable convolution neural network on FPGA is being reviewed due to its ability to reduce the number of model parameters and improve calculation speeds, which makes it widely used in mobile edge computing applications such as Xception [25] and MobileNet [26].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [24]
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“[21] proposed a FPGA-based depth wise separable CNN accelerator, where the number of model parameters are decreased and thus calculation speed is faster and suitable for mobile devices.”
BackgroundFPGA-Based Lightweight CNN Acceleration System for Real-Time Recognition
Ju, J., & Liu, C. (2024) · International Conference on Integrated Circuits and Microsystems (ICICM) · doi:10.1109/icicm63644.2024.10814533 · Cited by 4 · see citing works
Xiao, C., Xu, D., Qiu, S., Shi, C., & Ning, K. (2021) · IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA) · doi:10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00044 · Cited by 4 · see citing works
“While the partition scheme and scheduling scheme are not explained in [3].”
BackgroundMethodInfluentialNebula: A Scalable and Flexible Accelerator for DNN Multi-Branch Blocks on Embedded Systems
Yang, D., Li, X., Qi, L., Zhang, W., & Jiang, Z. (2022) · Electronics · doi:10.3390/electronics11040505 · Cited by 4 · see citing works
“…co-design to achieve orders of magnitude energy efficiency improvements over Attention (one of the most important recent advancements in DNNs [14]); and, Ding et al. (2019) use double-buffering-based memory channels to improve the system throughput and performance in Depthwise Conv [15].”
MethodCheng, X., Wang, Y., Ding, W., Lou, H., & Li, P. (2024) · Electronics · doi:10.3390/electronics13071217 · Cited by 4 · see citing works
Self-citationDSA-CNN: an fpga-integrated deformable systolic array for convolutional neural network acceleration
Wan, Y., Chen, J., Yang, X., Zhang, H., Huang, C., & Xie, X. (2024) · Applied Intelligence · doi:10.1007/s10489-024-05898-w · Cited by 4 · see citing works
“It differs from conventional convolution by processing each input channel separately and independently, rather than combining results across multiple channels [23, 24].”
Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays
Tufa, G. T., Andargie, F. A., & Bijalwan, A. (2022) · Computational Intelligence and Neuroscience · doi:10.1155/2022/8387364 · Cited by 4 · see citing works
“A variety of accelerators, including graphics processing units (GPUs), Field Programmable Gate Arrays, and application specific integrated circuits, has been used to increase the efficiency of CNNs [7–9].”
Comparative Evaluation between Accelerated RISC- V and ARM AI Inference Machines
Christofas, V., Amanatidis, P., Karampatzakis, D., Λάγκας, Θ., Goudos, S. K., Psannis, K. E., & Sarigiannidis, P. G. (2023) · World Symposium on Communication Engineering (WSCE) · doi:10.1109/wsce59557.2023.10365853 · Cited by 4 · see citing works
“When it comes to FPGAs, it is possible to design AI accelerators efficiently [14].”
BackgroundLiu, H., & Shen, C.-A. (2021) · Circuits Systems and Signal Processing · doi:10.1007/s00034-023-02331-4 · Cited by 3 · see citing works
“The number of MACs of each convolutional layer is computed as follows The depthwise separable convolution is proposed in [10] and is applied to MobileNet series [12, 13, 22].”
MethodLi, Q., Gao, M., Zhai, W., Wu, W., Wang, C., & Abdelmoniem, A. M. (2026) · Knowledge-Based Systems · doi:10.1016/j.knosys.2026.116300 · Cited by 2 · see citing works
A Cross-Attention Emotion Recognition Algorithm Based on Audio and Video Modalities
Wu, X., Mu, X., Qi, W., & Liu, X. (2024) · IEEE International Conference on Acoustics, Speech, and Signal Processing Workshops (ICASSPW) · doi:10.1109/icasspw62465.2024.10626511 · Cited by 2 · see citing works
“The Sconv unit is similar to the Bconv unit, but it uses a Depth Separable Convolution layer [16] with a convolution kernel size of 3×3 in the input.”
MethodLiying, C., Luo, F., Wang, F., & Lu, L. (2025) · Electronics · doi:10.3390/electronics14091740 · Cited by 2 · see citing works
Learning Engagement Assessment in MOOC Scenario
Rashmi Adyapady, R., & Annappa, B. (2022) · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · doi:10.1109/conecct55679.2022.9865699 · Cited by 2 · see citing works
“instead of a traditional convolution layer, resulting in reduced computational complexity and model size [21], [25].”
BackgroundVariyar, V. V. S., Aswin, S., Sowmya, V., Soman, K. P., Sivanpillai, R., & Brown, G. K. (2021) · The international archives of the photogrammetry, remote sensing and spatial information sciences/International archives of the photogrammetry, remote sensing and spatial information sciences · doi:10.5194/isprs-archives-xliv-m-3-2021-149-2021 · Cited by 2 · see citing works
CNNX: A Low Cost, CNN Accelerator for Embedded System in Vision at Edge
Farahani, A., Beitollahi, H., Fathi, M., & Barangi, R. (2022) · Arabian Journal for Science and Engineering · doi:10.1007/s13369-022-06931-1 · Cited by 2 · see citing works
“Most research studies have used depthwise separable convolution networks to reduce accelerator hardware size and speed up the execution [12,13].”
BackgroundD-DAGNet: AN IMPROVED HYBRID DEEP NETWORK FOR AUTOMATED CLASSIFICATION OF GLAUCOMA FROM OCT IMAGES
Sunija, A. P., Gopi, V. P., & Krishna, A. K. (2022) · Biomedical Engineering Applications Basis and Communications · doi:10.4015/s1016237222500429 · Cited by 2 · see citing works
Tikhonov, E. E., Александрович, Ч. К., & Burlyaeva, V. A. (2019) · International Multi-Conference on Industrial Engineering and Modern Technologies (FarEastCon) · doi:10.1109/fareastcon.2019.8934139 · Cited by 2 · see citing works
“It is known that the difference in FPGA and CPLD architectures causes different areas of their application: FPGA is used in the area where extremely high performance is required at significant logical volumes, CPLD is utilized in the area of small projects of digital logic schemes [20].”
Energy-Efficient Deep Learning for Cloud Detection Onboard Nanosatellite
Khalil, I., Daghouri, A., Chanoui, M. A., Guennoun, Z., & Addaim, A. (2025) · IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing · doi:10.1109/jstars.2025.3553304 · Cited by 1 · see citing works
Unified multimodal conditional framework for unsupervised anomaly detection
Nafti, N., Besbes, O., Abdallah, A. B., & Bedoui, M. H. (2025) · International Journal of Data Science and Analytics · doi:10.1007/s41060-025-00745-8 · Cited by 1 · see citing works
High Accuracy Individual Identification Method for Sea Turtles with Deep Learning
Nishida, K., Katayama, T., Song, T., & Nozawa, Y. (2025) · International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) · doi:10.1109/itc-cscc66376.2025.11137714 · Cited by 1 · see citing works
A Parallel Ring Streaming Dataflow-Based Convolution Array Architecture for CNN Accelerator
Jha, P. K., Shukla, S., & Ray, K. C. (2025) · IEEE Embedded Systems Letters · doi:10.1109/les.2025.3623654 · Cited by 1 · see citing works
“Ding et al. [2] proposed a custom convolution engine for depthwise separable convolution, implementing a fully unrolled hardware accelerator with dedicated hardware for all the layers.”
Vemuri, S. M., Gundrapally, A., Xia, Z., Kim, J., & Choi, K. K. (2026) · IEEE Access · doi:10.1109/access.2025.3650071 · Cited by 1 · see citing works
An FPGA based Method of Polynomial Multiplication
Xiao, X., Diao, W., He, A., & Wu, J. (2022) · Asia Conference on Algorithms, Computing and Machine Learning (CACML) · doi:10.1109/cacml55074.2022.00028 · Cited by 1 · see citing works
“As shown in Figure 8, the optimization process of the pipeline makes the calculation of matrix multiplication more efficient [35].”
MethodMethods and hardware to accelerate the work of a convolutional neural network
Tsmots, I., Berezsky, O., & Berezkyy, M. O. (2023) · Applied Aspects of Information Technology · doi:10.15276/aait.06.2023.1 · Cited by 1 · see citing works
On Determining Suitable Embedded Devices for Deep Learning Models
Padilla, D. E., Rashwan, H. A., & Puig, D. (2021) · Frontiers in artificial intelligence and applications · doi:10.3233/faia210147 · Cited by 1 · see citing works
“For instance, some works used Fourier Transforms [13], and binarized models [11] or even they have modified internal network architectures looking for faster operations [5].”
MethodBjerge, K., Schougaard, J. H., & Larsen, D. E. (2020) · arXiv (Cornell University)
An´alisis de desempe˜no de capas de CNN para arquitecturas heterog´eneas basadas en FPGAs usando HLS
Guerra-Londono, M., Castaño-Londoño, L., Alzate-Anzola, C., Márquez-Viloria, D., & Velásquez, R. A. (2020) · Ingeniería · doi:10.14483/23448393.15634
“La paralelización de las capas convolucionales en FPGA se ha realizado utilizando metodologı́as de diseño convencional RTL como en [5], [9], [3], [10], y herramientas de sı́ntesis de alto nivel (HLS) como en [13].”
BackgroundLiu, H., & Shen, C.-A. (2021) · SSRN Electronic Journal · doi:10.2139/ssrn.3992939
Design of YOLOv2-tiny accelerator based on PYNQ-Z2 platform
yixuan, Z., Hu, B., Liu, F., Yan, T., & Gao, H. (2023) · International Conference on Information Science, Electrical and Automation Engineering (ISEAE) · doi:10.1117/12.2689581
“Convolutional neural networks have emerged as a powerful tool for learning features from vast amounts of data, enabling recognition of similar types of data in a wide range of applications, particularly in the field of image recognition [1].”
BackgroundA Partial Method for Calculating CNN Networks Based On Loop Tiling
Farahani, A., Beitollahi, H., Fathy, M., & Barangi, R. (2023) · Sharq. · doi:10.61186/itrc.15.2.12
“Most research studies have used Depthwise Separable Convolution networks to reduce hardware size and speed up the execution [7], [9].”
MethodA related convolutional neural network for cancer diagnosis using microRNA data classification
Jaddi, N. S., Abdullah, S., Goh, S. L., & Hasan, M. K. (2024) · Healthcare Technology Letters · doi:10.1049/htl2.12097
Niranjen, R. K. M., Yogesh, C. K., Vinodh, A., Sureshkumar, T., & Vatchala, S. (2025) · IEEE Access · doi:10.1109/access.2025.3562595
“As such, this model introduced in this paper is an attempt to pose and preserve WaveNet’s core competencies with significantly reduced computational cost and memory interference [Figure 2] [24], [25].”
Co‐DeepNet: A Cooperative Convolutional Neural Network for DNA Methylation‐Based Age Prediction
Jaddi, N. S., Abadeh, M. S., Bagheri, N., Abdullah, S., Ariannejad, M., Nazri, M. Z. A., & Alvankarian, F. (2025) · CAAI Transactions on Intelligence Technology · doi:10.1049/cit2.70026
Yanamala, R. M. R., Muralidhar, P., & Raj, R. D. A. (2025) · Engineering Applications of Artificial Intelligence · doi:10.1016/j.engappai.2025.112975
A Resource-Efficient FPGA Architecture for Real-Time Classification of Optical Weather Images
Liying, C., Yuan, H., Luo, F., & Lu, L. (2026) · Photonics · doi:10.3390/photonics13100987
- Authors
- Ding, W., Huang, Z., Huang, Z., Tian, L., Wang, H., & Feng, S.
- Affiliations
- Chinese Academy of Sciences (CN)
- Corresponding author
- Wang, Hui
- Venue
- Journal of Systems Architecture
- Publisher
- Elsevier BV
- Published
- 2019-08
- Volume
- 97
- Pages
- 278-286
- ISSN
- 1383-7621 (ISSN-L)
- OpenAlex
- W2907579173
- Cited by
- 85
- References
- 48
- Citations by year
- 2026: 3 · 2025: 12 · 2024: 12 · 2023: 20 · 2022: 10 · 2021: 17 · 2020: 7 · 2019: 4
- FWCI
- 3.50
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- Journal of Systems Architecture (publishedVersion)
- Funders
- Shanghai Municipal Science and Technology Commission (18511111302)
- Chinese Academy of Sciences (184131KYSB20160018)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- depthwise separable convolution, FPGA accelerator, pipelined architecture, double buffering, memory channels, matrix multiplication, mobile edge computing, low-power inference
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