Ion traps fabricated in a CMOS foundry
Open accessAbstract
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.
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The use of advanced standard fabrication methods such as CMOS is facilitated, compared with rf traps, by the lack of high-voltage rf signals.
“The use of advanced standard fabrication methods such as CMOS56,57 is facilitated, compared with rf traps, by the lack of high-voltage rf signals.”
From Penning micro-trap for quantum computing (2024) · cites this paper as [56]
Cites
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Self-citationMaterials challenges and opportunities for quantum computing hardware
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Self-citationIon-trap measurements of electric-field noise near surfaces
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Self-citationIntegrated optical addressing of an ion qubit
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Self-citationShuttling-based trapped-ion quantum information processing
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“The use of advanced standard fabrication methods such as CMOS 56,57 is facilitated, compared with rf traps, by the lack of high-voltage rf signals.”
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Optimization and implementation of a surface-electrode ion trap junction
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Self-citation2022 Roadmap on integrated quantum photonics
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Self-citation
- Authors
- Mehta, K. K., Eltony, A. M., Bruzewicz, C. D., Chuang, I. L., Ram, R. J., Sage, J. M., & Chiaverini, J.
- Affiliations
- Massachusetts Institute of Technology (US)
- MIT-Harvard Center for Ultracold Atoms (US)
- MIT Lincoln Laboratory (US)
- Venue
- Applied Physics Letters
- Publisher
- AIP Publishing
- Published
- 2014-07-28
- Volume
- 105
- Issue
- 4
- ISSN
- 0003-6951 (ISSN-L)
- 1077-3118
- OpenAlex
- W2002255493
- Cited by
- 64
- References
- 3
- Citations by year
- 2026: 2 · 2025: 3 · 2024: 8 · 2023: 4 · 2022: 6 · 2021: 6 · 2020: 14 · 2019: 6 · 2018: 2 · 2017: 4 · 2016: 5 · 2015: 3 · 2014: 1
- FWCI
- 4.32
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Locations
- Applied Physics Letters (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- DSpace@MIT (Massachusetts Institute of Technology) (submittedVersion, cc-by-nc-sa)
- arXiv (Cornell University)
- Funders
- National Science Foundation (NSF)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Quantum Information and Cryptography
- Physical Sciences › Physics and Astronomy › Atomic and Molecular Physics, and Optics › Cold Atom Physics and Bose-Einstein Condensates
- Physical Sciences › Computer Science › Artificial Intelligence › Quantum Computing Algorithms and Architecture
- Keywords
- surface-electrode ion trap, CMOS foundry fabrication, trapped-ion quantum computing, ion trapping, motional heating, ion loading
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