The DOI matches its Crossref record; 6 of the 6 references it cites were found in a registry or an index.
Towards efficient deep neural network training by FPGA-based batch-level parallelism
Open accessAbstract
Abstract Training deep neural networks (DNNs) requires a significant amount of time and resources to obtain acceptable results, which severely limits its deployment in resource-limited platforms. This paper proposes DarkFPGA, a novel customizable framework to efficiently accelerate the entire DNN training on a single FPGA platform. First, we explore batch-level parallelism to enable efficient FPGA-based DNN training. Second, we devise a novel hardware architecture optimised by a batch-oriented data pattern and tiling techniques to effectively exploit parallelism. Moreover, an analytical model is developed to determine the optimal design parameters for the DarkFPGA accelerator with respect to a specific network specification and FPGA resource constraints. Our results show that the accelerator is able to perform about 10 times faster than CPU training and about a third of the energy consumption than GPU training using 8-bit integers for training VGG-like networks on the CIFAR dataset for the Maxeler MAX5 platform.
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“In addition, batch-oriented data patterns, which refer to channel height width batch (CHWB) patterns, are implemented, using batch level parallelism but utilizing bandwidth as a compromise.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Batch-oriented data patterns and tiling techniques are used to optimize the hardware accelerator, which is able to effectively exploit parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Both forward and backward propagation on a homogenous FPGA system were able to improve the training by using a DarkFPGA accelerator with batch level parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
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Metadata
- Authors
- Luo, C., Sit, M.-K., Fan, H., Liu, S., Luk, W., & Guo, C.
- Affiliations
- Fudan University (CN)
- Imperial College London (GB)
- Venue
- Journal of Semiconductors
- Publisher
- IOP Publishing
- Published
- 2020-02-01
- Volume
- 41
- Issue
- 2
- Pages
- 022403
- ISSN
- 1674-4926 (ISSN-L)
- 2058-6140
- OpenAlex
- W3004303566
- Cited by
- 26
- References
- 6
- Citations by year
- 2025: 2 · 2024: 4 · 2023: 7 · 2022: 8 · 2021: 3 · 2020: 2
- FWCI
- 4.20
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Licence
- Locations
- Journal of Semiconductors (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- FPGA, deep neural network training, hardware accelerators, tiling, energy efficiency, VGG, resource-constrained platforms
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