The DOI matches its Crossref record; 6 of the 6 references it cites were found in a registry or an index.
Towards efficient deep neural network training by FPGA-based batch-level parallelism
Open accessAbstract
Abstract Training deep neural networks (DNNs) requires a significant amount of time and resources to obtain acceptable results, which severely limits its deployment in resource-limited platforms. This paper proposes DarkFPGA, a novel customizable framework to efficiently accelerate the entire DNN training on a single FPGA platform. First, we explore batch-level parallelism to enable efficient FPGA-based DNN training. Second, we devise a novel hardware architecture optimised by a batch-oriented data pattern and tiling techniques to effectively exploit parallelism. Moreover, an analytical model is developed to determine the optimal design parameters for the DarkFPGA accelerator with respect to a specific network specification and FPGA resource constraints. Our results show that the accelerator is able to perform about 10 times faster than CPU training and about a third of the energy consumption than GPU training using 8-bit integers for training VGG-like networks on the CIFAR dataset for the Maxeler MAX5 platform.
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“In addition, batch-oriented data patterns, which refer to channel height width batch (CHWB) patterns, are implemented, using batch level parallelism but utilizing bandwidth as a compromise.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Batch-oriented data patterns and tiling techniques are used to optimize the hardware accelerator, which is able to effectively exploit parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Both forward and backward propagation on a homogenous FPGA system were able to improve the training by using a DarkFPGA accelerator with batch level parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
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Cites
Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks
Ren, S., He, K., Girshick, R., & Sun, J. (2017) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2016.2577031 · Cited by 73,472
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Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
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Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al. (2015) · International Journal of Computer Vision · doi:10.1007/s11263-015-0816-y · Cited by 39,380
Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator
Matsumoto, M., & Nishimura, T. (1998) · ACM Transactions on Modeling and Computer Simulation · doi:10.1145/272991.272995 · Cited by 5,780
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Zhang, C., Sun, G., Fang, Z., Zhou, P., Pan, P., & Cong, J. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2785257 · Cited by 270
Maximum Performance Computing with Dataflow Engines
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Research works printed but not linked: 1
- Krishnan, 2017, Accelerator templates and runtime support for variable precision CNN, CISC Workshop
Cited by
Sorted by citations
Duan, Q., Huang, J., Hu, S., Deng, R., Lu, Z., & Yu, S. (2023) · IEEE Communications Surveys & Tutorials · doi:10.1109/comst.2023.3316615 · Cited by 189
Embedded Intelligence on FPGA: Survey, Applications and Challenges
Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105
“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
MethodA Systematic Literature Review on Binary Neural Networks
Sayed, R., Azmi, H., Shawkey, H., Khalil, A. H., & Refky, M. A. (2023) · IEEE Access · doi:10.1109/access.2023.3258360 · Cited by 51
FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory
Venkataramanaiah, S. K., Suh, H.-S., Yin, S., Nurvitadhi, E., Dasu, A. R., Cao, Y. K., & Seo, J.-S. (2020) · doi:10.1145/3400302.3415643 · Cited by 33
Tang, Y., Zhang, X., Zhou, P., & Hu, J. (2022) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3505633 · Cited by 26
Metadata
- Authors
- Luo, C., Sit, M.-K., Fan, H., Liu, S., Luk, W., & Guo, C.
- Affiliations
- Fudan University (CN)
- Imperial College London (GB)
- Venue
- Journal of Semiconductors
- Publisher
- IOP Publishing
- Published
- 2020-02-01
- Volume
- 41
- Issue
- 2
- Pages
- 022403
- ISSN
- 1674-4926 (ISSN-L)
- 2058-6140
- OpenAlex
- W3004303566
- Cited by
- 26
- References
- 6
- Citations by year
- 2025: 2 · 2024: 4 · 2023: 7 · 2022: 8 · 2021: 3 · 2020: 2
- FWCI
- 4.20
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Licence
- Locations
- Journal of Semiconductors (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- FPGA, deep neural network training, hardware accelerators, tiling, energy efficiency, VGG, resource-constrained platforms
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