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Cited by 34Quantum Computing Algorithms and ArchitectureQuantum Information and CryptographyQuantum many-body systems

A small quantum computer is needed to optimize fault-tolerant protocols

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Iyer, Pavithran, Poulin, David·2018·Quantum Science and Technology
DOI 10.1088/2058-9565/aab73c
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Abstract

As far as we know, a useful quantum computer will require fault-tolerant gates, and existing schemes demand a prohibitively large space and time overhead. We argue that a first generation quantum computer will be very valuable to design, test, and optimize fault-tolerant protocols tailored to the noise processes of the hardware. Our argument is essentially a critical analysis of the current methods envisioned to optimize fault-tolerant schemes, which rely on hardware characterization, noise modeling, and numerical simulations. We show that, even within a very restricted set of noise models, error-correction protocols depend strongly on the details of the noise model. Combined to the intrinsic difficulty of hardware characterization and of numerical simulations of fault-tolerant protocols, we arrive at the conclusion that the currently envisioned optimization cycle is of very limited scope. On the other hand, the direct characterization of a fault-tolerant scheme on a small quantum computer bypasses these difficulties, and could provide a bootstrapping path to full-scale fault-tolerant quantum computation.

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  • Empirically, the logical circuit is much more tolerant to coherent errors than the physical implementation.

    “First, empirically, it seems that the logical circuit is much more tolerant to coherent errors49,110,111, and understanding the manifestations of this is a subject of continuing investigation.”

    From Logical quantum processor based on reconfigurable atom arrays (2024) · cites this paper as [111]

    The paper’s ‘Simulating quantum mechanics’ section identifies systematic rotations as coherent errors, and ‘Standard error metrics’ compares physical noise strength with resulting logical noise. But the simulations model initial memory errors with noiseless correction gates (Section II); they do not establish that a logical circuit is much more tolerant of coherent errors than a physical circuit implementation. (LLM, conf=0.78)

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Related

Authors
Iyer, P., & Poulin, D.
Affiliations
Université de Sherbrooke (CA)
ORCID
Iyer, Pavithran
Venue
Quantum Science and Technology
Publisher
IOP Publishing
Published
2018-06-19
Volume
3
Issue
3
Pages
030504
ISSN
2058-9565 (ISSN-L)
DOI
10.1088/2058-9565/aab73c
OpenAlex
W2770964512
Cited by
34
References
55
Citations by year
2025: 4 · 2023: 3 · 2022: 6 · 2021: 5 · 2020: 9 · 2019: 5 · 2018: 2
FWCI
2.92
Type
journal article
Language
en
Open access
Licence
Locations
  • Quantum Science and Technology (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • arXiv (Cornell University)
Funders
Army Research Office (W911NF-14-C-0048, W911NF)
Topics
  • Physical Sciences › Computer Science › Artificial Intelligence › Quantum Computing Algorithms and Architecture
  • Physical Sciences › Computer Science › Artificial Intelligence › Quantum Information and Cryptography
  • Physical Sciences › Physics and Astronomy › Atomic and Molecular Physics, and Optics › Quantum many-body systems
Keywords
fault-tolerant quantum computing, noise models, hardware characterization, bootstrapping

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