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Low-power CMOS digital design
Abstract
Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.>
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Citations
Cited by
(2006) · Cited by 1,979
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., & Yamada, J. (1995) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.400426 · Cited by 1,123
A dynamic voltage scaled microprocessor system
Burd, T. D., Pering, T. A., Stratakos, A. J., & Brodersen, R. W. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.881202 · Cited by 916
Self-citationAnalog Versus Digital: Extrapolating from Electronics to Neurobiology
Sarpeshkar, R. (1998) · Neural Computation · doi:10.1162/089976698300017052 · Cited by 496
A Self-Tuning DVS Processor Using Delay-Error Detection and Correction
Das, S., Roberts, D., Lee, S., Pant, S., Blaauw, D., Austin, T., Flautner, K., & Mudge, T. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.870912 · Cited by 396
Metadata
- Authors
- Chandrakasan, A. P., Sheng, S., & Brodersen, R. W.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 1992-04
- Volume
- 27
- Issue
- 4
- Pages
- 473-484
- ISSN
- 0018-9200 (ISSN-L)
- OpenAlex
- W1633471522
- Cited by
- 2,156
- References
- 0
- FWCI
- 59.70
- Type
- journal article
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: Low-power CMOS digital design. https://app.cochat.ai/papers/10.1109/4.126534
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- Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low-power CMOS digital design. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/4.126534
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