The DOI matches its Crossref record; 7 of the 7 references it cites were found in a registry or an index.
A dynamic voltage scaled microprocessor system
Abstract
A microprocessor system is presented in which the supply voltage and clock frequency can be dynamically varied so that the system can deliver high throughput when required while significantly extending battery life during the low speed periods. The system consists of a dc-dc switching regulator, an ARM V4 microprocessor with a 16-kB cache, a bank of 64-kB SRAM ICs, and an I/O interface IC. The four custom chips were fabricated in a standard 0.6-/spl mu/m 3-metal CMOS process. The system can dynamically vary the supply voltage from 1.2 to 3.8 V in less than 70 /spl mu/s. This provides a throughput range of 6-85 MIPS with an energy consumption of 0.54-5.6 mW/MIP yielding an effective energy efficiency as high as 26200 MIPS/W.
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Cites
Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (2015) · Cited by 2,232
Self-citationChandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.126534 · Cited by 2,156
Self-citationDigital integrated circuits : a design perspective
Rabaey, J. M., Chandrakasan, A. P., & Nikolić, B. (1996) · CERN Document Server (European Organization for Nuclear Research) · Cited by 2,118
CMOS scaling for high performance and low power-the next ten years
Davari, B., Dennard, R. H., & Shahidi, G. G. (1995) · Proceedings of the IEEE · doi:10.1109/5.371968 · Cited by 386
Design issues for dynamic voltage scaling
Burd, T. D., & Brodersen, R. W. (2000) · Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00 · doi:10.1145/344166.344181 · Cited by 363
Self-citationDesign issues for Dynamic Voltage Scaling
Burd, T. D., & Brodersen, R. W. (2000) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1109/lpe.2000.155245 · Cited by 141
Self-citationA variable-frequency parallel I/O interface with adaptive power-supply regulation
Wei, G.-Y., Kim, J., Liu, D., Sidiropoulos, S., & Horowitz, M. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.881205 · Cited by 119
Cited by
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003) · Proceedings of the IEEE · doi:10.1109/jproc.2002.808156 · Cited by 2,368
A Self-Tuning DVS Processor Using Delay-Error Detection and Correction
Das, S., Roberts, D., Lee, S., Pant, S., Blaauw, D., Austin, T., Flautner, K., & Mudge, T. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.870912 · Cited by 396
On the Carbon Footprint Optimization in an InterCloud Environment
Justafort, V. D., Beaubrun, R., & Pierre, S. (2018) · IEEE Transactions on Cloud Computing · doi:10.1109/tcc.2015.2511768 · Cited by 10
Metadata
- Authors
- Burd, T. D., Pering, T. A., Stratakos, A. J., & Brodersen, R. W.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2000-11
- Volume
- 35
- Issue
- 11
- Pages
- 1571-1580
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2133079932
- Cited by
- 916
- References
- 7
- FWCI
- 51.54
- Type
- journal article
- Language
- en
- Open access
- closed
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