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Cited by 419

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A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

Young, I.A., Greason, J.K., Wong, K.L.·1992·IEEE Journal of Solid-State Circuits

Abstract

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency.>

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Metadata

Authors
Young, I. A., Greason, J. K., & Wong, K. L.
Venue
IEEE Journal of Solid-State Circuits
Published
1992-11
Volume
27
Issue
11
Pages
1599-1607
ISSN
  • 0018-9200 (ISSN-L)
  • 1558-173X
OpenAlex
W3142075743
Cited by
419
References
0
FWCI
8.40
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. https://app.cochat.ai/papers/10.1109/4.165341
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Young, I. A., Greason, J. K., & Wong, K. L. (1992). A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/4.165341

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