Jitter in ring oscillators

Analysis and Design of Analog Integrated Circuits

Betts, W. R. (1978) · Electronics and Power · doi:10.1049/ep.1978.0296 · Cited by 3,837 · see citing works

Analysis and Design of Analog Integrated Circuits

Gray, P. R., & Meyer, R. G. (1977) · Cited by 3,482 · see citing works

A simple model of feedback oscillator noise spectrum

Leeson, D. B. (1966) · Proceedings of the IEEE · doi:10.1109/proc.1966.4682 · Cited by 2,462 · see citing works

Phaselock Techniques

Gardner, F. M. (1984) · Wiley eBooks · doi:10.1002/0471732699 · Cited by 1,699 · see citing works

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

Young, I. A., Greason, J., & Wong, K. L. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.165341 · Cited by 418 · see citing works

Analysis of timing jitter in CMOS ring oscillators

Weigandt, T. C., Kim, B., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409188 · Cited by 287 · see citing works

Noise in relaxation oscillators

Abidi, A. A., & Meyer, R. G. (1983) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1983.1052034 · Cited by 228 · see citing works

Noise in Oscillators

Edson, W. A. (1960) · Proceedings of the IRE · doi:10.1109/jrproc.1960.287573 · Cited by 213 · see citing works

PLL/DLL system noise analysis for low jitter clock synthesizer design

Kim, B., Weigandt, T. C., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409189 · Cited by 142 · see citing works

A 1.8-GHz monolithic LC voltage-controlled oscillator

Nguyen, N., & Meyer, R. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.121569 · Cited by 128 · see citing works

A 200-MHz CMOS phase-locked loop with dual phase detectors

Ware, K. M., Lee, H.-S., & Sodini, C. G. (1989) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.44991 · Cited by 98 · see citing works

A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors

Buchwald, A., Martin, K. W., Oki, A. K., & Kobayashi, K. W. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.173102 · Cited by 80 · see citing works

Jitter in ring oscillators

McNeill, J. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409561 · Cited by 74 · see citing works

A high-frequency electronically tunable quadrature oscillator

Verhoeven, C. J. M. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.142608 · Cited by 63 · see citing works

A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission

Banu, M., & Dunlop, A. E. (1993) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1993.280066 · Cited by 62 · see citing works

MOS oscillators with multi-decade tuning range and gigahertz maximum speed

Banu, M. (1988) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.90035 · Cited by 62 · see citing works

A 52MHz And 155MHz Clock-recovery PLL

DeVito, L., Newton, J. W., Croughwell, R., Bulzacchelli, J. F., & Benkley, F. (1991) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1991.689101 · Cited by 61 · see citing works

A PLL clock generator with 5 to 110 MHz lock range for microprocessors

Young, I. A., Greason, J., Smith, J. E., & Wong, K. L. (2003) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1992.200405 · Cited by 54 · see citing works

A 300-MHz CMOS voltage-controlled ring oscillator

Enam, S. K., & Abidi, A. A. (1990) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.50320 · Cited by 52 · see citing works

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

Ransijn, H., & O'Connor, P. (1991) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.90084 · Cited by 51 · see citing works

A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit

Lai, B., & Walker, R. C. (1991) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1991.689102 · Cited by 50 · see citing works

PLL design for a 500 MB/s interface

Horowitz, M., Chan, A., Cobrunson, J., Gasbarro, J. A., Lee, T. H., Leung, W., Richardson, W., Thrush, T. P., & Fujii, Y. (1993) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1993.280015 · Cited by 48 · see citing works

Noise characteristics of current mirror sinks/sources

Bilotti, A., & Mariani, E. (1975) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1975.1050652 · Cited by 41 · see citing works

A new low-noise 100-MHz balanced relaxation oscillator

Sneep, J., & Verhoeven, C. J. M. (1990) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.102662 · Cited by 39 · see citing works

A 50 MHz phase- and frequency-locked loop

Cordell, R. R., Forney, J. B., Dunn, C. N., & Garrett, W. G. (1979) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1979.1051309 · Cited by 37 · see citing works

First order oscillators

Verhoeven, C. J. M. (1990) · Research Repository (Delft University of Technology) · Cited by 29 · see citing works

A two-chip CMOS read channel for hard-disk drives

Negahban, M., Behrashi, R., Tsang, G., Abouhossein, H., & Bouchaya, G. (1993) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1993.280042 · Cited by 28 · see citing works

Monochromaticity and Noise in a Regenerative Electrical Oscillator

Golay, M. E. (1960) · Proceedings of the IRE · doi:10.1109/jrproc.1960.287575 · Cited by 28 · see citing works

An accurate analytical propagation delay model for high-speed CML bipolar circuits

Sharaf, K. M., & Elmasry, M. I. (1994) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.272092 · Cited by 27 · see citing works

The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters and on Oversampling Delta Sigma ADCs

Harris, S. D. (1990) · Journal of the Audio Engineering Society · Cited by 26 · see citing works

A low-power 128-MHz VCO for monolithic PLL ICs

Kato, K., Sase, T., Sato, H., Ikushima, I., & Kojima, S. (1988) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.1009 · Cited by 25 · see citing works

A 1.8 GHz monolithic LC voltage-controlled oscillator

Nguyen, N. M., & Meyer, R. G. (2003) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1992.200460 · Cited by 24 · see citing works

How to achieve optimum performance from delta-sigma A/D and D/A converters

Harris, S. D. (1993) · Journal of the Audio Engineering Society · Cited by 19 · see citing works

A fully-integrated HIFI PLL FM-demodulator

Sempel, A., & van Nieuwenburg, H. (1990) · doi:10.1109/isscc.1990.110149 · Cited by 19 · see citing works

A 33mb/s Data Synchronizing Phase-locked-loop Circuit

Llewellyn, Wong, Tietz, & Tucci (1988) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1988.663590 · Cited by 17 · see citing works

A 200 MHz CMOS phase-locked loop with dual phase detectors

Ware, K. M., Lee, H.-S., & Sodini, C. G. (2003) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1989.48255 · Cited by 11 · see citing works

A 16 Mb/s data detector and timing recovery circuit for token ring LAN

Scott, J., Starke, R., Ramachandran, R., Pietruszynki, D., Bell, S., McClellan, K. J., & Thompson, K. (2003) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1989.48237 · Cited by 10 · see citing works

A monolithic 2.3 Gb/s 100 mW clock and data recovery circuit

Soyuer, M., & Ainspan, H. A. (1993) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1993.280016 · Cited by 10 · see citing works

Interpolating ring VCO with V -to- f linearity compensation

McNeill, J. (1994) · Electronics Letters · doi:10.1049/el:19941384 · Cited by 7 · see citing works

A monolithic 480 Mb/s parallel AGC/decision/clock-recovery circuit in 1.2 mu m CMOS

Hu, T. H., & Gray, P. R. (1993) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.1993.280068 · Cited by 7 · see citing works

Jitter and phase noise in ring oscillators

Hajimiri, A., Limotyrakis, S., & Lee, T. H. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.766813 · Cited by 1,071 · see citing works

Phase Noise and Jitter in CMOS Ring Oscillators

Abidi, A. A. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.876206 · Cited by 740 · see citing works

A study of oscillator jitter due to supply and substrate noise

Herzel, F., & Razavi, B. (1999) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/82.749085 · Cited by 316 · see citing works

Analysis and modeling of bang-bang clock and data recovery circuits

Lee, J., Kundert, K., & Razavi, B. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.831600 · Cited by 238 · see citing works

A low-noise fast-lock phase-locked loop with adaptive bandwidth control

Lee, J., & Kim, B. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.859502 · Cited by 238 · see citing works

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

Xiao, J., Peterchev, A. V., Zhang, J., & Sanders, S. R. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.836353 · Cited by 237 · see citing works

Integrated GHz Voltage Controlled Oscillators

Kinget, P. R. (1999) · Springer eBooks · doi:10.1007/978-1-4757-3047-0_17 · Cited by 225 · see citing works

Joint Estimation of Channel and Oscillator Phase Noise in MIMO Systems

Mehrpouyan, H., Nasir, A. A., Blostein, S. D., Eriksson, T., Karagiannidis, G. K., & Svensson, T. (2012) · IEEE Transactions on Signal Processing · doi:10.1109/tsp.2012.2202652 · Cited by 151 · see citing works

Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers

Kundert, K. (2009) · Cited by 147 · see citing works

RF Impairments in Wireless Transceivers: Phase Noise, CFO, and IQ Imbalance – A Survey

Mohammadian, A., & Tellambura, C. (2021) · IEEE Access · doi:10.1109/access.2021.3101845 · Cited by 136 · see citing works

Calculation of the Performance of Communication Systems From Measured Oscillator Phase Noise

Khanzadi, M. R., Kuylenstierna, D., Panahi, A., Eriksson, T., & Zirath, H. (2014) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2013.2285698 · Cited by 133 · see citing works

A jitter characterization system using a component-invariant Vernier delay line

Chan, A. H., & Roberts, G. W. (2004) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2003.820531 · Cited by 130 · see citing works

Phase noise in digital frequency dividers

Levantino, S., Romano, L., Pellerano, S., Samori, C., & Lacaita, A. L. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.826338 · Cited by 121 · see citing works

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability

Larsson, P. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.808920 · Cited by 120 · see citing works

Jitter optimization based on phase-locked loop design parameters

Mansuri, M., & Yang, C.-K. K. (2002) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.803935 · Cited by 118 · see citing works

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

Casper, B. K., & O’Mahony, F. (2009) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2008.931647 · Cited by 116 · see citing works

Virtual damping and einstein relation in oscillators

Ham, D., & Hajimiri, A. (2003) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.808283 · Cited by 114 · see citing works

Prospects of CMOS technology for high-speed optical communication circuits

Razavi, B. (2002) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.801195 · Cited by 112 · see citing works

Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers

(2009) · Institute of Electrical and Electronics Engineers eBooks · doi:10.1109/9780470545492.ch5 · Cited by 99 · see citing works

Analysis of jitter in phase-locked loops

Lee, D. C. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.807265 · Cited by 96 · see citing works

Noise in phase-locked loops

Hajimiri, A. (2002) · Southwest Symposium on Mixed-Signal Design · doi:10.1109/ssmsd.2001.914927 · Cited by 95 · see citing works

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Elshazly, A., Inti, R., Young, B., & Hanumolu, P. K. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2254552 · Cited by 93 · see citing works

A Power-Harvesting Pad-Less Millimeter-Sized Radio

Tabesh, M., Dolatsha, N., Arbabian, A., & Niknejad, A. M. (2015) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2014.2384034 · Cited by 91 · see citing works

A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines

Szplet, R., Jachna, Z., Kwiatkowski, P., & Różyc, K. (2013) · Measurement Science and Technology · doi:10.1088/0957-0233/24/3/035904 · Cited by 85 · see citing works

Clock Jitter Effects on Sampling: A Tutorial

Leme, C. A. (2011) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2011.942067 · Cited by 81 · see citing works

True Random Number Generators Using Electrical Noise

Gong, L., Zhang, J., Liu, H., Sang, L., & Wang, Y. (2019) · IEEE Access · doi:10.1109/access.2019.2939027 · Cited by 77 · see citing works

Measurements and analysis of PLL jitter caused by digital switching noise

Larsson, P. (2001) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.933469 · Cited by 77 · see citing works

An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

Szplet, R., & Klepacki, K. (2009) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2009.2027777 · Cited by 76 · see citing works

Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-$N$ PLLs

Herzel, F., Osmany, S. A., & Scheytt, J. C. (2010) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2009.2039832 · Cited by 73 · see citing works

A CMOS Self-Regulating VCO With Low Supply Sensitivity

Hwang, I.-C., Kim, C. H., & Kang, S. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2003.820881 · Cited by 70 · see citing works

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

Niitsu, K., Sakurai, M., Harigai, N., YAMAGUCHI, T. J., & Kobayashi, H. (2012) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2012.2211655 · Cited by 68 · see citing works

Optimization of phase-locked loop circuits via geometric programming

Colleran, D. M., Portmann, C. L., Hassibi, A., Crusius, C. A. R., Mohan, S. S., Boyd, S., Lee, T. H., & Hershenson, M. D. M. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2003.1249422 · Cited by 68 · see citing works

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

Brownlee, M., Hanumolu, P. K., Mayaram, K., & Moon, U.-K. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.884194 · Cited by 62 · see citing works

A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends

Sivaraaj, N. R., & Majeed, K. K. A. (2023) · IEEE Access · doi:10.1109/access.2023.3331308 · Cited by 60 · see citing works

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

Hanumolu, P. K., Kratyuk, V., Wei, G.-Y., & Moon, U.-K. (2008) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.914287 · Cited by 59 · see citing works

Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

Djahanshahi, H., & Salama, C. A. T. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.845188 · Cited by 59 · see citing works

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

Levantino, S., Marucci, G., Marzin, G., Fenaroli, A., Samori, C., & Lacaita, A. L. (2015) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2015.2473667 · Cited by 58 · see citing works

Oscillation frequency in CML and ESCL ring oscillators

Alioto, M., & Palumbo, G. (2001) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/81.904885 · Cited by 57 · see citing works

A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$m CMOS With ${-}$70 dBc Reference Spur

Maulik, P. C., & Mercer, D. A. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.900300 · Cited by 54 · see citing works

Phase noise in multi-gigahertz CMOS ring oscillators

Hajimiri, A., Limotyrakis, S., & Lee, T. H. (2002) · Custom Integrated Circuits Conference · doi:10.1109/cicc.1998.694905 · Cited by 53 · see citing works

Channel Estimation, Carrier Recovery, and Data Detection in the Presence of Phase Noise in OFDM Relay Systems

Wang, R., Mehrpouyan, H., Tao, M., & Hua, Y. (2015) · IEEE Transactions on Wireless Communications · doi:10.1109/twc.2015.2487268 · Cited by 50 · see citing works

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Galton, I., & Weltin-Wu, C. (2018) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2018.2856247 · Cited by 50 · see citing works

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

Williams, S. L., Thompson, H., Hufford, M., & Naviasky, E. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2004.1358761 · Cited by 50 · see citing works

A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links

Toifl, T., Menolfi, C., Buchmann, P., Kossel, M., Morf, T., Reutemann, R., Ruegg, M., Schmatz, M., & Weiss, J. (2005) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2005.856581 · Cited by 48 · see citing works

An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

Zhang, J., & Zhou, D. (2017) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2017.2769239 · Cited by 46 · see citing works

Distributed Differential Oscillators for Global Clock Networks

Chan, S. C., Shepard, K. L., & Restle, P. J. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.880610 · Cited by 46 · see citing works

Jitter in oscillators with 1/f noise sources

Liu, C., & McNeill, J. (2004) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2004.1328309 · Cited by 44 · see citing works

A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging

Arbabian, A., Callender, S., Kang, S., Afshar, B., Chien, J., & Niknejad, A. M. (2010) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2010.2077150 · Cited by 44 · see citing works

A Novel Model on Phase Noise of Ring Oscillator Based on Last Passage Time

Leung, B. (2004) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2004.823658 · Cited by 42 · see citing works

Chaotic synchronization of three coupled oscillators with ring connection

Kyprianidis, I. M., & Stouboulos, I. N. (2003) · Chaos Solitons & Fractals · doi:10.1016/s0960-0779(02)00361-2 · Cited by 41 · see citing works

An Analysis of Phase Noise in Realigned VCOs

Dalt, N. D. (2014) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2013.2296195 · Cited by 40 · see citing works

Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise

Homayoun, A., & Razavi, B. (2014) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2289893 · Cited by 39 · see citing works

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

Zanchi, A., & Tsay, F. (2005) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2005.848020 · Cited by 38 · see citing works

Survey of integrated‐circuit‐oscillator phase‐noise analysis

Pankratz, E. J., & Sánchez‐Sinencio, E. (2013) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.1890 · Cited by 37 · see citing works

Design and Optimization of Multipath Ring Oscillators

Hafez, A. A., & Yang, C.-K. K. (2011) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2011.2142810 · Cited by 36 · see citing works

Spectral analysis of time-domain phase jitter measurements

Moon, U.-K., Mayaram, K., & Stonick, J. T. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.802343 · Cited by 36 · see citing works

Analysis of timing jitter in ring oscillators due to power supply noise

Pialis, T., & Phang, K. (2003) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2003.1205656 · Cited by 36 · see citing works

A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link

O’Mahony, F., Mansuri, M., Casper, B. K., Jaussi, J. E., & Mooney, R. (2006) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2006.1705296 · Cited by 35 · see citing works

Modeling Jitter in PLL-based Frequency Synthesizers

Kundert, K. (2001) · Cited by 34 · see citing works

Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection

Viera, R., Maurine, P., Dutertre, J.-M., & Bastos, R. P. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2928972 · Cited by 32 · see citing works

Phase Noise and Jitter

Poore, R., & Eda, A. E. (2001) · Cited by 32 · see citing works

A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link

Rao, A., Mansour, M., Singh, G., Lim, C.-H., Ahmed, R., & Johnson, D. R. (2008) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2008.2001870 · Cited by 31 · see citing works

On-Chip Voltage Reference-Based Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Measurements

Nissinen, I., & Kostamovaara, J. (2008) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2008.2005857 · Cited by 31 · see citing works

On models, bounds, and estimation algorithms for time-varying phase noise

Khanzadi, M. R., Mehrpouyan, H., Alpman, E., Svensson, T., Kuylenstierna, D., & Eriksson, T. (2011) · International Conference on Signal Processing and Communication Systems · doi:10.1109/icspcs.2011.6140897 · Cited by 29 · see citing works

A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System

Wang, X. Y., Dokania, R., & Apsel, A. (2013) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2013.2239094 · Cited by 29 · see citing works

CMOS high-speed I/Os - present and future

Lee, M.-J. E., Dally, W. J., Farjad-Rad, R., Ng, H.-T., Senthinathan, R., Edmondson, J. H., & Poulton, J. W. (2004) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd.2003.1240940 · Cited by 28 · see citing works

A 7.5 ps single-shot precision integrated time counter with segmented delay line

Klepacki, K., Szplet, R., & Pelka, R. (2014) · Review of Scientific Instruments · doi:10.1063/1.4868500 · Cited by 27 · see citing works

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

Marinov, O., Deen, M. J., & Jiménez-Tejada, J. A. (2022) · Physics Reports · doi:10.1016/j.physrep.2022.06.005 · Cited by 27 · see citing works

The effect of supply and substrate noise on jitter in ring oscillators

Barton, N., Ozis, D., Fiez, T. S., & Mayaram, K. (2003) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2002.1012890 · Cited by 26 · see citing works

A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments

Cervelli, G., Marchioro, A., & Moreira, P. (2004) · IEEE Transactions on Nuclear Science · doi:10.1109/tns.2004.829551 · Cited by 26 · see citing works

Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source

Guler, U., & Dundar, G. (2014) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2013.2283993 · Cited by 25 · see citing works

Differential Ring Oscillator Based Capacitance Sensor for Microfluidic Applications

Mohammad, K., & Thomson, D. J. (2017) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2016.2616346 · Cited by 25 · see citing works

Control linearity and jitter of relaxation oscillators

Gierkink, S. L. J. (1999) · doi:10.3990/1.9789036513173 · Cited by 25 · see citing works

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

Zhang, J., & Zhou, D. (2014) · Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment · doi:10.1016/j.nima.2014.10.040 · Cited by 24 · see citing works

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling

Zanchi, A., & Samori, C. (2008) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2008.916576 · Cited by 23 · see citing works

Bit-Error-Rate Estimation for High-Speed Serial Links

Hong, D., Ong, C.-K., & Cheng, K.-T. T. (2006) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2006.883852 · Cited by 23 · see citing works

Methodology for on-chip adaptive jitter minimization in phase-locked loops

Mansuri, M., Hadiashar, A., & Yang, C.-K. K. (2003) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2003.819124 · Cited by 23 · see citing works

Low-Power Low-Jitter On-Chip Clock Generation

Ángeles, L. (2003) · Cited by 23 · see citing works

Design of high-speed circuits for optical communication systems

Razavi, B. (2002) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2001.929789 · Cited by 21 · see citing works

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

Choe, W., Lee, B.-J., Kim, J., Jeong, D., & Kim, G. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.903038 · Cited by 20 · see citing works

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters

Parekh, P., Yuan, F., & Zhou, Y. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3122340 · Cited by 20 · see citing works

Investigation of Phase Noise of Ring Oscillators With Time-Varying Current and Noise Sources by time-scaling Thermal Noise

Leung, B., & McLeish, D. L. (2004) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2004.835688 · Cited by 20 · see citing works

Wireline equalization using pulse-width modulation

Schrader, J.-R., Klumperink, E. A. M., Visschers, J. L., & Nauta, B. (2006) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2006.320827 · Cited by 20 · see citing works

Generation of accurate on-chip time constants and stable transconductances

McLaren, A., & Martin, K. (2001) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.913748 · Cited by 20 · see citing works

Crystal oscillators' jitter measurements and its estimation of phase noise

Zamek, I. G., & Zamek, S. (2004) · Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium (EFTF/IFCS) · doi:10.1109/freq.2003.1275150 · Cited by 19 · see citing works

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Kougianos, E., & Mohanty, S. P. (2008) · Microelectronics Journal · doi:10.1016/j.mejo.2008.08.017 · Cited by 19 · see citing works

A wide range PLL for 64X speed CD-ROMs & 10X speed DVD-ROMs

Lee, J., Jin, W. K., Choi, D. M., Lee, G. S., & Kim, S. (2000) · IEEE Transactions on Consumer Electronics · doi:10.1109/30.883399 · Cited by 19 · see citing works

An integrated CMOS PLL for low-jitter applications

Herzel, F., Fischer, G., Gustat, H., & Weger, P. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.802965 · Cited by 19 · see citing works

A digital-pll-based true random number generator

Liu, C., & McNeill, J. (2005) · Research in Microelectronics and Electronics, 2005 PhD · doi:10.1109/rme.2005.1543017 · Cited by 18 · see citing works

An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

Chang, Y.-S., Lin, C.-L., Wang, W.-S., Lee, C.-C., & Shih, C.-Y. (2006) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2006.880035 · Cited by 18 · see citing works

Numerical Jitter Minimization for PLL-Based FMCW Radar Systems

Herzel, F., Waldmann, S., & Kissinger, D. (2019) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2019.2893891 · Cited by 17 · see citing works

A Power-Efficient Clock and Data Recovery Circuit in 0.18 $\mu{\hbox {m}}$ CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Tajalli, A., Müller, P. F., & Leblebici, Y. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.905234 · Cited by 17 · see citing works

Effects of deterministic jitter in a cable on jitter tolerance measurements

YAMAGUCHI, T. J., Soma, M., Ishidal, M., Kurosawa, M., & Musha, H. (2004) · IEEE International Test Conference (ITC) · doi:10.1109/test.2003.1270825 · Cited by 17 · see citing works

An integrated 10 GHz quadrature LC-VCO in SiGe:C BiCMOS - technology for low-jitter applications

Herzel, F., Winkler, W. G., & Borngräber, J. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2003.1249406 · Cited by 17 · see citing works

A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction

Wu, Y., Lu, P., & Staszewski, R. B. (2020) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2020.2983581 · Cited by 16 · see citing works

All-digital successive approximation TDC in time-mode signal processing

Lee, D. J., Yuan, F., & Zhou, Y. (2021) · Microelectronics Journal · doi:10.1016/j.mejo.2021.105152 · Cited by 16 · see citing works

On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models

Haddad, P., Teglia, Y., Bernard, F., & Fischer, V. (2014) · doi:10.5555/2616606.2616655 · Cited by 16 · see citing works

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Ghoneima, M., Ismail, Y., Khellah, M. M., & De, V. K. (2007) · VLSI design · doi:10.1155/2007/95402 · Cited by 16 · see citing works

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning

Brownlee, M., Hanumolu, P. K., Mayaram, K., & Moon, U.-K. (2006) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2006.1696305 · Cited by 16 · see citing works

Reduction of the 1/f noise induced phase noise in a CMOS ring oscillator by increasing the amplitude of oscillation

Gierkink, S. L. J., van der Wel, A. P., Hoogzaad, G., Klumperink, E. A. M., & van Tuijl, A. J. M. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1998.704241 · Cited by 16 · see citing works

Analysis of jitter in ring oscillators

McNeill, J., & Ricketts, D. S. (2009) · Springer eBooks · doi:10.1007/978-0-387-76528-0_6 · Cited by 3 · see citing works

Jitter and phase noise in ring oscillators

Hajimiri, A., Limotyrakis, S., & Lee, T. H. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.766813 · Cited by 1,071 · see citing works

Jitter analysis of ring oscillator in a PLL

Cheng, J., Milor, L. S., Ho, S.-F., & Huang, H. (2006) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas.2003.1562257 · Cited by 1 · see citing works

Jitter performance in high speed oscillators

Chen, Y. (1998) · Iowa State University Digital Repository (Iowa State University)

Prediction of phase noise and jitter in ring oscillators

Barton, N. (2002)