The DOI matches its Crossref record; 40 of the 40 references it cites were found in a registry or an index.
Jitter in ring oscillators
Abstract
Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Citations
Cites
Analysis and Design of Analog Integrated Circuits
Betts, W. R. (1978) · Electronics and Power · doi:10.1049/ep.1978.0296 · Cited by 3,837
Analysis and Design of Analog Integrated Circuits
Gray, P. R., & Meyer, R. G. (1977) · Cited by 3,482
A simple model of feedback oscillator noise spectrum
Leeson, D. B. (1966) · Proceedings of the IEEE · doi:10.1109/proc.1966.4682 · Cited by 2,462
Gardner, F. M. (1984) · Wiley eBooks · doi:10.1002/0471732699 · Cited by 1,699
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
Young, I. A., Greason, J., & Wong, K. L. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.165341 · Cited by 418
Analysis of timing jitter in CMOS ring oscillators
Weigandt, T. C., Kim, B., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409188 · Cited by 287
Noise in relaxation oscillators
Abidi, A. A., & Meyer, R. G. (1983) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1983.1052034 · Cited by 228
Edson, W. A. (1960) · Proceedings of the IRE · doi:10.1109/jrproc.1960.287573 · Cited by 213
PLL/DLL system noise analysis for low jitter clock synthesizer design
Kim, B., Weigandt, T. C., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409189 · Cited by 142
A 1.8-GHz monolithic LC voltage-controlled oscillator
Nguyen, N., & Meyer, R. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.121569 · Cited by 128
Flagged first, then by citations
Research works printed but not linked: 5
- 10.1109/ISCAS.1994.409561 · DOI
- gardner, 1990, synchronous optical network (sonet) transport systems—common generic criteria, Bellcore Tech Advisory, ta nwt 253
- kim, 1993, CSA803 User s Guide
- gray, 0, AD807 data sheet
- stuck, 1969, Switching-time jitter statistics for bipolar transistor threshold-crossing detectors
Cited by
Sorted by citations
Jitter and phase noise in ring oscillators
Hajimiri, A., Limotyrakis, S., & Lee, T. H. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.766813 · Cited by 1,071
Phase Noise and Jitter in CMOS Ring Oscillators
Abidi, A. A. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.876206 · Cited by 740
A study of oscillator jitter due to supply and substrate noise
Herzel, F., & Razavi, B. (1999) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/82.749085 · Cited by 316
Analysis and modeling of bang-bang clock and data recovery circuits
Lee, J., Kundert, K., & Razavi, B. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.831600 · Cited by 238
A low-noise fast-lock phase-locked loop with adaptive bandwidth control
Lee, J., & Kim, B. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.859502 · Cited by 238
Metadata
- Authors
- McNeill, J. A.
- Affiliations
- Worcester Polytechnic Institute (US)
- Corresponding author
- McNeill, J.A.
- ORCID
- McNeill, J.A.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 1997-06
- Volume
- 32
- Issue
- 6
- Pages
- 870-879
- ISSN
- 0018-9200 (ISSN-L)
- OpenAlex
- W2119123494
- Cited by
- 342
- References
- 40
- Citations by year
- 2026: 3 · 2025: 1 · 2024: 9 · 2023: 11 · 2022: 10 · 2021: 11 · 2020: 3 · 2019: 12 · 2018: 10 · 2017: 10 · 2016: 5 · 2015: 8 · 2014: 15 · 2013: 15 · 2012: 10
- FWCI
- 8.51
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in PLL and VCO Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- ring oscillator, jitter, phase-locked loop, clock recovery, thermal noise, shot noise, bipolar integrated circuits
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review