Cited by 342Advancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignAnalog and Mixed-Signal Circuit Design

The DOI matches its Crossref record; 40 of the 40 references it cites were found in a registry or an index.

Jitter in ring oscillators

McNeill, J.A.·1997·IEEE Journal of Solid-State Circuits

DOI 10.1109/4.585289

Open this paper in CoChat — free account

Abstract

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

Integrity signals

Registry

Crossref · 10.1109/4.585289

Cites

40 of 40 references verified0 citation errors · 0 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Claims the paper makes

This paper’s full text isn’t openly available, so its claims and self-check weren’t run. The registry and citation checks still apply.

Analysis and Design of Analog Integrated Circuits
Betts, W. R. (1978) · Electronics and Power · doi:10.1049/ep.1978.0296 · Cited by 3,837
Analysis and Design of Analog Integrated Circuits
Gray, P. R., & Meyer, R. G. (1977) · Cited by 3,482
A simple model of feedback oscillator noise spectrum
Leeson, D. B. (1966) · Proceedings of the IEEE · doi:10.1109/proc.1966.4682 · Cited by 2,462
Phaselock Techniques
Gardner, F. M. (1984) · Wiley eBooks · doi:10.1002/0471732699 · Cited by 1,699
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
Young, I. A., Greason, J., & Wong, K. L. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.165341 · Cited by 418
Analysis of timing jitter in CMOS ring oscillators
Weigandt, T. C., Kim, B., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409188 · Cited by 287
Noise in relaxation oscillators
Abidi, A. A., & Meyer, R. G. (1983) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1983.1052034 · Cited by 228
Noise in Oscillators
Edson, W. A. (1960) · Proceedings of the IRE · doi:10.1109/jrproc.1960.287573 · Cited by 213
PLL/DLL system noise analysis for low jitter clock synthesizer design
Kim, B., Weigandt, T. C., & Gray, P. R. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1994.409189 · Cited by 142
A 1.8-GHz monolithic LC voltage-controlled oscillator
Nguyen, N., & Meyer, R. (1992) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.121569 · Cited by 128

Show all 40 references

Research works printed but not linked: 5

10.1109/ISCAS.1994.409561 · DOI
gardner, 1990, synchronous optical network (sonet) transport systems—common generic criteria, Bellcore Tech Advisory, ta nwt 253
kim, 1993, CSA803 User s Guide
gray, 0, AD807 data sheet
stuck, 1969, Switching-time jitter statistics for bipolar transistor threshold-crossing detectors

Sorted by citations

Jitter and phase noise in ring oscillators
Hajimiri, A., Limotyrakis, S., & Lee, T. H. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.766813 · Cited by 1,071
Phase Noise and Jitter in CMOS Ring Oscillators
Abidi, A. A. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.876206 · Cited by 740
A study of oscillator jitter due to supply and substrate noise
Herzel, F., & Razavi, B. (1999) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/82.749085 · Cited by 316
Analysis and modeling of bang-bang clock and data recovery circuits
Lee, J., Kundert, K., & Razavi, B. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.831600 · Cited by 238
A low-noise fast-lock phase-locked loop with adaptive bandwidth control
Lee, J., & Kim, B. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.859502 · Cited by 238
A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications
Xiao, J., Peterchev, A. V., Zhang, J., & Sanders, S. R. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.836353 · Cited by 237
Integrated GHz Voltage Controlled Oscillators
Kinget, P. R. (1999) · Springer eBooks · doi:10.1007/978-1-4757-3047-0_17 · Cited by 225
Joint Estimation of Channel and Oscillator Phase Noise in MIMO Systems
Mehrpouyan, H., Nasir, A. A., Blostein, S. D., Eriksson, T., Karagiannidis, G. K., & Svensson, T. (2012) · IEEE Transactions on Signal Processing · doi:10.1109/tsp.2012.2202652 · Cited by 151
Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers
Kundert, K. (2009) · Cited by 147
RF Impairments in Wireless Transceivers: Phase Noise, CFO, and IQ Imbalance – A Survey
Mohammadian, A., & Tellambura, C. (2021) · IEEE Access · doi:10.1109/access.2021.3101845 · Cited by 136
Calculation of the Performance of Communication Systems From Measured Oscillator Phase Noise
Khanzadi, M. R., Kuylenstierna, D., Panahi, A., Eriksson, T., & Zirath, H. (2014) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2013.2285698 · Cited by 133
A jitter characterization system using a component-invariant Vernier delay line
Chan, A. H., & Roberts, G. W. (2004) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2003.820531 · Cited by 130
Phase noise in digital frequency dividers
Levantino, S., Romano, L., Pellerano, S., Samori, C., & Lacaita, A. L. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2004.826338 · Cited by 121
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability
Larsson, P. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.808920 · Cited by 120
Jitter optimization based on phase-locked loop design parameters
Mansuri, M., & Yang, C.-K. K. (2002) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.803935 · Cited by 118
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial
Casper, B. K., & O’Mahony, F. (2009) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2008.931647 · Cited by 116
Virtual damping and einstein relation in oscillators
Ham, D., & Hajimiri, A. (2003) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.808283 · Cited by 114
Prospects of CMOS technology for high-speed optical communication circuits
Razavi, B. (2002) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.801195 · Cited by 112
Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers
(2009) · Institute of Electrical and Electronics Engineers eBooks · doi:10.1109/9780470545492.ch5 · Cited by 99
Analysis of jitter in phase-locked loops
Lee, D. C. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.807265 · Cited by 96
Noise in phase-locked loops
Hajimiri, A. (2002) · Southwest Symposium on Mixed-Signal Design · doi:10.1109/ssmsd.2001.914927 · Cited by 95
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
Elshazly, A., Inti, R., Young, B., & Hanumolu, P. K. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2254552 · Cited by 93
A Power-Harvesting Pad-Less Millimeter-Sized Radio
Tabesh, M., Dolatsha, N., Arbabian, A., & Niknejad, A. M. (2015) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2014.2384034 · Cited by 91
A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines
Szplet, R., Jachna, Z., Kwiatkowski, P., & Różyc, K. (2013) · Measurement Science and Technology · doi:10.1088/0957-0233/24/3/035904 · Cited by 85
Clock Jitter Effects on Sampling: A Tutorial
Leme, C. A. (2011) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2011.942067 · Cited by 81
True Random Number Generators Using Electrical Noise
Gong, L., Zhang, J., Liu, H., Sang, L., & Wang, Y. (2019) · IEEE Access · doi:10.1109/access.2019.2939027 · Cited by 77
Measurements and analysis of PLL jitter caused by digital switching noise
Larsson, P. (2001) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.933469 · Cited by 77
An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking
Szplet, R., & Klepacki, K. (2009) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2009.2027777 · Cited by 76
Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-$N$ PLLs
Herzel, F., Osmany, S. A., & Scheytt, J. C. (2010) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2009.2039832 · Cited by 73
A CMOS Self-Regulating VCO With Low Supply Sensitivity
Hwang, I.-C., Kim, C. H., & Kang, S. (2004) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2003.820881 · Cited by 70
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation
Niitsu, K., Sakurai, M., Harigai, N., YAMAGUCHI, T. J., & Kobayashi, H. (2012) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2012.2211655 · Cited by 68
Optimization of phase-locked loop circuits via geometric programming
Colleran, D. M., Portmann, C. L., Hassibi, A., Crusius, C. A. R., Mohan, S. S., Boyd, S., Lee, T. H., & Hershenson, M. D. M. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2003.1249422 · Cited by 68
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning
Brownlee, M., Hanumolu, P. K., Mayaram, K., & Moon, U.-K. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.884194 · Cited by 62
A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends
Sivaraaj, N. R., & Majeed, K. K. A. (2023) · IEEE Access · doi:10.1109/access.2023.3331308 · Cited by 60
A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter
Hanumolu, P. K., Kratyuk, V., Wei, G.-Y., & Moon, U.-K. (2008) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.914287 · Cited by 59
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications
Djahanshahi, H., & Salama, C. A. T. (2000) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.845188 · Cited by 59
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
Levantino, S., Marucci, G., Marzin, G., Fenaroli, A., Samori, C., & Lacaita, A. L. (2015) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2015.2473667 · Cited by 58
Oscillation frequency in CML and ESCL ring oscillators
Alioto, M., & Palumbo, G. (2001) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/81.904885 · Cited by 57
A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$m CMOS With ${-}$70 dBc Reference Spur
Maulik, P. C., & Mercer, D. A. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.900300 · Cited by 54
Phase noise in multi-gigahertz CMOS ring oscillators
Hajimiri, A., Limotyrakis, S., & Lee, T. H. (2002) · Custom Integrated Circuits Conference · doi:10.1109/cicc.1998.694905 · Cited by 53
Channel Estimation, Carrier Recovery, and Data Detection in the Presence of Phase Noise in OFDM Relay Systems
Wang, R., Mehrpouyan, H., Tao, M., & Hua, Y. (2015) · IEEE Transactions on Wireless Communications · doi:10.1109/twc.2015.2487268 · Cited by 50
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement
Galton, I., & Weltin-Wu, C. (2018) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2018.2856247 · Cited by 50
An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter
Williams, S. L., Thompson, H., Hufford, M., & Naviasky, E. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2004.1358761 · Cited by 50
A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links
Toifl, T., Menolfi, C., Buchmann, P., Kossel, M., Morf, T., Reutemann, R., Ruegg, M., Schmatz, M., & Weiss, J. (2005) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2005.856581 · Cited by 48
An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA
Zhang, J., & Zhou, D. (2017) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2017.2769239 · Cited by 46
Distributed Differential Oscillators for Global Clock Networks
Chan, S. C., Shepard, K. L., & Restle, P. J. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.880610 · Cited by 46
Jitter in oscillators with 1/f noise sources
Liu, C., & McNeill, J. (2004) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2004.1328309 · Cited by 44
Self-citation
A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging
Arbabian, A., Callender, S., Kang, S., Afshar, B., Chien, J., & Niknejad, A. M. (2010) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2010.2077150 · Cited by 44
A Novel Model on Phase Noise of Ring Oscillator Based on Last Passage Time
Leung, B. (2004) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2004.823658 · Cited by 42
Chaotic synchronization of three coupled oscillators with ring connection
Kyprianidis, I. M., & Stouboulos, I. N. (2003) · Chaos Solitons & Fractals · doi:10.1016/s0960-0779(02)00361-2 · Cited by 41
An Analysis of Phase Noise in Realigned VCOs
Dalt, N. D. (2014) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2013.2296195 · Cited by 40
Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise
Homayoun, A., & Razavi, B. (2014) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2289893 · Cited by 39
A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter
Zanchi, A., & Tsay, F. (2005) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2005.848020 · Cited by 38
Survey of integrated‐circuit‐oscillator phase‐noise analysis
Pankratz, E. J., & Sánchez‐Sinencio, E. (2013) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.1890 · Cited by 37
Design and Optimization of Multipath Ring Oscillators
Hafez, A. A., & Yang, C.-K. K. (2011) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2011.2142810 · Cited by 36
Spectral analysis of time-domain phase jitter measurements
Moon, U.-K., Mayaram, K., & Stonick, J. T. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.802343 · Cited by 36
Analysis of timing jitter in ring oscillators due to power supply noise
Pialis, T., & Phang, K. (2003) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2003.1205656 · Cited by 36
A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link
O’Mahony, F., Mansuri, M., Casper, B. K., Jaussi, J. E., & Mooney, R. (2006) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2006.1705296 · Cited by 35
Modeling Jitter in PLL-based Frequency Synthesizers
Kundert, K. (2001) · Cited by 34
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection
Viera, R., Maurine, P., Dutertre, J.-M., & Bastos, R. P. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2928972 · Cited by 32
Phase Noise and Jitter
Poore, R., & Eda, A. E. (2001) · Cited by 32
A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link
Rao, A., Mansour, M., Singh, G., Lim, C.-H., Ahmed, R., & Johnson, D. R. (2008) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2008.2001870 · Cited by 31
On-Chip Voltage Reference-Based Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Measurements
Nissinen, I., & Kostamovaara, J. (2008) · IEEE Transactions on Instrumentation and Measurement · doi:10.1109/tim.2008.2005857 · Cited by 31
On models, bounds, and estimation algorithms for time-varying phase noise
Khanzadi, M. R., Mehrpouyan, H., Alpman, E., Svensson, T., Kuylenstierna, D., & Eriksson, T. (2011) · International Conference on Signal Processing and Communication Systems · doi:10.1109/icspcs.2011.6140897 · Cited by 29
A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System
Wang, X. Y., Dokania, R., & Apsel, A. (2013) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2013.2239094 · Cited by 29
CMOS high-speed I/Os - present and future
Lee, M.-J. E., Dally, W. J., Farjad-Rad, R., Ng, H.-T., Senthinathan, R., Edmondson, J. H., & Poulton, J. W. (2004) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd.2003.1240940 · Cited by 28
A 7.5 ps single-shot precision integrated time counter with segmented delay line
Klepacki, K., Szplet, R., & Pelka, R. (2014) · Review of Scientific Instruments · doi:10.1063/1.4868500 · Cited by 27
Low-frequency noise in downscaled silicon transistors: Trends, theory and practice
Marinov, O., Deen, M. J., & Jiménez-Tejada, J. A. (2022) · Physics Reports · doi:10.1016/j.physrep.2022.06.005 · Cited by 27
The effect of supply and substrate noise on jitter in ring oscillators
Barton, N., Ozis, D., Fiez, T. S., & Mayaram, K. (2003) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2002.1012890 · Cited by 26
A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments
Cervelli, G., Marchioro, A., & Moreira, P. (2004) · IEEE Transactions on Nuclear Science · doi:10.1109/tns.2004.829551 · Cited by 26
Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source
Guler, U., & Dundar, G. (2014) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2013.2283993 · Cited by 25
Differential Ring Oscillator Based Capacitance Sensor for Microfluidic Applications
Mohammad, K., & Thomson, D. J. (2017) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2016.2616346 · Cited by 25
Control linearity and jitter of relaxation oscillators
Gierkink, S. L. J. (1999) · doi:10.3990/1.9789036513173 · Cited by 25
A new delay line loops shrinking time-to-digital converter in low-cost FPGA
Zhang, J., & Zhou, D. (2014) · Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment · doi:10.1016/j.nima.2014.10.040 · Cited by 24
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling
Zanchi, A., & Samori, C. (2008) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2008.916576 · Cited by 23
Bit-Error-Rate Estimation for High-Speed Serial Links
Hong, D., Ong, C.-K., & Cheng, K.-T. T. (2006) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2006.883852 · Cited by 23
Methodology for on-chip adaptive jitter minimization in phase-locked loops
Mansuri, M., Hadiashar, A., & Yang, C.-K. K. (2003) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2003.819124 · Cited by 23
Low-Power Low-Jitter On-Chip Clock Generation
Ángeles, L. (2003) · Cited by 23
Design of high-speed circuits for optical communication systems
Razavi, B. (2002) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2001.929789 · Cited by 21
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme
Choe, W., Lee, B.-J., Kim, J., Jeong, D., & Kim, G. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.903038 · Cited by 20
Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters
Parekh, P., Yuan, F., & Zhou, Y. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3122340 · Cited by 20
Investigation of Phase Noise of Ring Oscillators With Time-Varying Current and Noise Sources by time-scaling Thermal Noise
Leung, B., & McLeish, D. L. (2004) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2004.835688 · Cited by 20
Wireline equalization using pulse-width modulation
Schrader, J.-R., Klumperink, E. A. M., Visschers, J. L., & Nauta, B. (2006) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2006.320827 · Cited by 20
Generation of accurate on-chip time constants and stable transconductances
McLaren, A., & Martin, K. (2001) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.913748 · Cited by 20
Crystal oscillators' jitter measurements and its estimation of phase noise
Zamek, I. G., & Zamek, S. (2004) · Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium (EFTF/IFCS) · doi:10.1109/freq.2003.1275150 · Cited by 19
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO
Kougianos, E., & Mohanty, S. P. (2008) · Microelectronics Journal · doi:10.1016/j.mejo.2008.08.017 · Cited by 19
A wide range PLL for 64X speed CD-ROMs & 10X speed DVD-ROMs
Lee, J., Jin, W. K., Choi, D. M., Lee, G. S., & Kim, S. (2000) · IEEE Transactions on Consumer Electronics · doi:10.1109/30.883399 · Cited by 19
An integrated CMOS PLL for low-jitter applications
Herzel, F., Fischer, G., Gustat, H., & Weger, P. (2002) · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · doi:10.1109/tcsii.2002.802965 · Cited by 19
A digital-pll-based true random number generator
Liu, C., & McNeill, J. (2005) · Research in Microelectronics and Electronics, 2005 PhD · doi:10.1109/rme.2005.1543017 · Cited by 18
Self-citation
An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators
Chang, Y.-S., Lin, C.-L., Wang, W.-S., Lee, C.-C., & Shih, C.-Y. (2006) · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · doi:10.1109/tcsi.2006.880035 · Cited by 18
Numerical Jitter Minimization for PLL-Based FMCW Radar Systems
Herzel, F., Waldmann, S., & Kissinger, D. (2019) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2019.2893891 · Cited by 17
A Power-Efficient Clock and Data Recovery Circuit in 0.18 $\mu{\hbox {m}}$ CMOS Technology for Multi-Channel Short-Haul Optical Data Communication
Tajalli, A., Müller, P. F., & Leblebici, Y. (2007) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.905234 · Cited by 17
Effects of deterministic jitter in a cable on jitter tolerance measurements
YAMAGUCHI, T. J., Soma, M., Ishidal, M., Kurosawa, M., & Musha, H. (2004) · IEEE International Test Conference (ITC) · doi:10.1109/test.2003.1270825 · Cited by 17
An integrated 10 GHz quadrature LC-VCO in SiGe:C BiCMOS - technology for low-jitter applications
Herzel, F., Winkler, W. G., & Borngräber, J. (2004) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2003.1249406 · Cited by 17
A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction
Wu, Y., Lu, P., & Staszewski, R. B. (2020) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2020.2983581 · Cited by 16
All-digital successive approximation TDC in time-mode signal processing
Lee, D. J., Yuan, F., & Zhou, Y. (2021) · Microelectronics Journal · doi:10.1016/j.mejo.2021.105152 · Cited by 16
On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models
Haddad, P., Teglia, Y., Bernard, F., & Fischer, V. (2014) · doi:10.5555/2616606.2616655 · Cited by 16
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme
Ghoneima, M., Ismail, Y., Khellah, M. M., & De, V. K. (2007) · VLSI design · doi:10.1155/2007/95402 · Cited by 16
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning
Brownlee, M., Hanumolu, P. K., Mayaram, K., & Moon, U.-K. (2006) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2006.1696305 · Cited by 16
Reduction of the 1/f noise induced phase noise in a CMOS ring oscillator by increasing the amplitude of oscillation
Gierkink, S. L. J., van der Wel, A. P., Hoogzaad, G., Klumperink, E. A. M., & van Tuijl, A. J. M. (2002) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.1998.704241 · Cited by 16

Authors: McNeill, J. A.
Affiliations: Worcester Polytechnic Institute (US)
Corresponding author: McNeill, J.A.
ORCID: McNeill, J.A.
Venue: IEEE Journal of Solid-State Circuits
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Published: 1997-06
Volume: 32
Issue: 6
Pages: 870-879
ISSN: 0018-9200 (ISSN-L)
DOI: 10.1109/4.585289
OpenAlex: W2119123494
Cited by: 342
References: 40
Citations by year: 2026: 3 · 2025: 1 · 2024: 9 · 2023: 11 · 2022: 10 · 2021: 11 · 2020: 3 · 2019: 12 · 2018: 10 · 2017: 10 · 2016: 5 · 2015: 8 · 2014: 15 · 2013: 15 · 2012: 10
FWCI: 8.51
Type: journal article
Language: en
Open access: closed
Licence: ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html (vor)
Locations: IEEE Journal of Solid-State Circuits (publishedVersion)
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in PLL and VCO Technologies
Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
Keywords: ring oscillator, jitter, phase-locked loop, clock recovery, thermal noise, shot noise, bipolar integrated circuits

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review

Jitter in ring oscillators

Abstract

Overview

Integrity signals

Verification

Claims the paper makes

Citations

Cites

Cited by

Related

Metadata

Record

About these checks