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Cited by 665

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A case for intelligent RAM

Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., Yelick, K.·1997·IEEE Micro

Abstract

Two trends call into question the current practice of fabricating microprocessors and DRAMs as different chips on different fabrication lines. The gap between processor and DRAM speed is growing at 50% per year; and the size and organization of memory on a single DRAM chip is becoming awkward to use, yet size is growing at 60% per year. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, and improve energy efficiency. It also allows more flexible selection of memory size and organization, and promises savings in board area. This article reviews the state of microprocessors and DRAMs today, explores some of the opportunities and challenges for IRAMs, and finally estimates performance and energy efficiency of three IRAM designs.

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Metadata

Authors
Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., & Yelick, K.
Venue
IEEE Micro
Published
1997
Volume
17
Issue
2
Pages
34-44
ISSN
0272-1732 (ISSN-L)
OpenAlex
W2112980698
Cited by
665
References
0
FWCI
35.50
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: A case for intelligent RAM. https://app.cochat.ai/papers/10.1109/40.592312
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Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., & Yelick, K. (1997). A case for intelligent RAM. IEEE Micro. https://doi.org/10.1109/40.592312

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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.