The DOI matches its Crossref record; 14 of the 14 references it cites were found in a registry or an index.
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
Abstract
Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.
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Cites
Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey
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1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing
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A Case for Intelligent RAM: IRAM
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A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing
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A 65 nm 0.165 fJ/Bit/Search 256$\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables
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A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS
Hayashi, I., Amano, T., Watanabe, N., Yano, Y., Kuroda, Y., Shirata, M., DOSAKA, K., Nii, K., 野田, 英., & Kawai, H. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2274888 · Cited by 86
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13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM
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Cited by
Memory devices and applications for in-memory computing
Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R., & Eleftheriou, E. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0655-z · Cited by 2,289
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
Agrawal, A., Jaiswal, A., Lee, C., & Roy, K. (2018) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2018.2848999 · Cited by 325
Wang, J., Wang, X., Eckert, C., Subramaniyan, A., Das, R., Blaauw, D., & Sylvester, D. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2939682 · Cited by 244
Self-citationXue, C.-X., Chiu, Y.-C., Liu, T.-W., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Wei, S.-Y., Lee, C.-Y., et al. (2020) · Nature Electronics · doi:10.1038/s41928-020-00505-5 · Cited by 181
Computing in memory with FeFETs
Reis, D., Niemier, M., & Hu, X. S. (2018) · Proceedings of the International Symposium on Low Power Electronics and Design · doi:10.1145/3218603.3218640 · Cited by 102
Metadata
- Authors
- Jeloka, S., Akesh, N. B., Sylvester, D., & Blaauw, D.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2016-04
- Volume
- 51
- Issue
- 4
- Pages
- 1009-1021
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2331783522
- Cited by
- 361
- References
- 14
- FWCI
- 32.90
- Type
- journal article
- Language
- en
- Open access
- closed
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