ESD: a pervasive reliability concern for IC technologies
Abstract
Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed.>
Integrity signals
Registry
Cites
Statistics
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
Vulnerability to electrostatic discharge from a charged human operator or during machine-based assembly is a critical consideration for neural amplifier ICs, especially in dry environments.
“Vulnerability to an electrostatic discharge (ESD) from a charged human operator or during machine-based assembly processes is another critical consideration [33, 115]. This is a particularly serious problem when the amplifier IC is used in dry environments, such as in the operating theater or in dry climates.”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [33]
Cites
Wunsch, D. C., & Bell, R. (1968) · IEEE Transactions on Nuclear Science · doi:10.1109/tns.1968.4325054 · Cited by 413 · see citing works
Thermal failure in semiconductor devices
Dwyer, V. M., Franklin, A., & Campbell, D. S. (1990) · Solid-State Electronics · doi:10.1016/0038-1101(90)90239-b · Cited by 216 · see citing works
Pulse Power Failure Modes in Semiconductors
Tasca, D. M. (1970) · IEEE Transactions on Nuclear Science · doi:10.1109/tns.1970.4325819 · Cited by 171 · see citing works
Polgreen, T., & Chatterjee, A. (1992) · IEEE Transactions on Electron Devices · doi:10.1109/16.121697 · Cited by 155 · see citing works
An analytical breakdown model for short-channel MOSFET's
Hsu, F.-C., Ko, P. K., Tam, S. M., et al. (1982) · IEEE Transactions on Electron Devices · doi:10.1109/t-ed.1982.21018 · Cited by 131 · see citing works
Dynamic gate coupling of NMOS for efficient output ESD protection
Duvvury, C., & Diaz, C. H. (1992) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/relphy.1992.187639 · Cited by 131 · see citing works
Self-citationAmerasekera, A., van Roozendaal, L., Bruines, J. J. P., et al. (1991) · IEEE Transactions on Electron Devices · doi:10.1109/16.83744 · Cited by 114 · see citing works
Self-citationESD failure modes: characteristics mechanisms, and process influences
Amerasekera, A., van den Abeelen, W., van Roozendaal, L., et al. (1992) · IEEE Transactions on Electron Devices · doi:10.1109/16.121703 · Cited by 81 · see citing works
Self-citationRountree, R. N., & Hutchins, C. L. (1985) · IEEE Transactions on Electron Devices · doi:10.1109/t-ed.1985.22047 · Cited by 80 · see citing works
Titanium disilicide contact resistivity and its impact on 1-µm CMOS circuit performance
Scott, D. B., Chapman, R. A., Wei, C.-C., et al. (1987) · IEEE Transactions on Electron Devices · doi:10.1109/t-ed.1987.22964 · Cited by 78 · see citing works
Internal chip ESD phenomena beyond the protection circuit
Duvvury, C., Rountree, R. N., & Adams, O. (1988) · IEEE Transactions on Electron Devices · doi:10.1109/16.8787 · Cited by 76 · see citing works
Self-citationChen, K. L. (1988) · IEEE Transactions on Electron Devices · doi:10.1109/16.8788 · Cited by 67 · see citing works
VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs
Hsu, F.-C., Ko, P. K., Tam, S. M., et al. (1982) · IEEE Transactions on Electron Devices · doi:10.1109/t-ed.1982.20998 · Cited by 60 · see citing works
ESD protection for submicron CMOS circuits-issues and solutions
Rountree, R. N. (2003) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.1988.32881 · Cited by 50 · see citing works
ESD Phenomena and Protection Issues in CMOS Output Buffers
Duvvury, C., Rountree, R. N., Fong, Y. X., et al. (1987) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.1987.362175 · Cited by 46 · see citing works
Self-citationESD Phenomena in Graded Junction Devices
Duvvury, C., Rountree, R. N., Stiegler, H. J., et al. (1989) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.1989.363364 · Cited by 39 · see citing works
Self-citationA low-voltage triggering SCR for on-chip ESD protection at output and input pads
Chatterjee, A., & Polgreen, T. (1990) · Symposium on VLSI Technology · doi:10.1109/vlsit.1990.111015 · Cited by 35 · see citing works
A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress
Guggenmos, X., & Holzner, R. (1992) · Journal of Electrostatics · doi:10.1016/0304-3886(92)90004-d · Cited by 24 · see citing works
Electrostatic discharge protection for one micron CMOS devices and circuits
Chen, K.-L., Giles, G., & Scott, D. B. (1986) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.1986.191226 · Cited by 22 · see citing works
ESD phenomena in graded junction devices
Duvvury, C., Rountree, R. N., Stiegler, H. J., et al. (2003) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/relphy.1989.36320 · Cited by 22 · see citing works
Self-citationHot Electron Reliability and ESD Latent Damage
Aur, S., Chatterjee, A., & Polgreen, T. (1988) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.1988.362193 · Cited by 18 · see citing works
Electrothermal simulation tools for analysis and design of ESD protection devices (NMOSFET)
Mayaram, K., Chern, J.-H., Arledge, L. A., et al. (2002) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.1991.235278 · Cited by 11 · see citing works
Amerasekera, A., & Chatterjee, A. (1993) · Journal of Electrostatics · doi:10.1016/0304-3886(93)90006-s · Cited by 8 · see citing works
Self-citationHot electron reliability and ESD latent damage
Aur, S., Chatterjee, A., & Polgreen, T. (2003) · doi:10.1109/relphy.1988.23418 · Cited by 6 · see citing works
Latent failures due to ESD in CMOS integrated circuits
Greason, W. D., Kucerovsky, Z., & Chum, K. W. K. (2003) · doi:10.1109/ias.1989.96902 · Cited by 5 · see citing works
Flagged first, then by citations
Cited by
Sorted by citations
Implantable neurotechnologies: a review of integrated circuit neural amplifiers
Ng, K. A., Greenwald, E., Xu, Y. P., & Thakor, N. V. (2016) · Medical & Biological Engineering & Computing · doi:10.1007/s11517-015-1431-3 · Cited by 83 · see citing works
- Authors
- Duvvury, C., & Amerasekera, A.
- Affiliations
- Texas Instruments (United States) (US)
- Venue
- Proceedings of the IEEE
- Published
- 1993-05
- Volume
- 81
- Issue
- 5
- Pages
- 690-702
- ISSN
- 0018-9219 (ISSN-L)
- OpenAlex
- W2170466905
- Cited by
- 148
- References
- 25
- Citations by year
- 2026: 2 · 2025: 5 · 2023: 4 · 2022: 3 · 2021: 3 · 2019: 2 · 2017: 3 · 2016: 3 · 2014: 2 · 2013: 1 · 2012: 3
- FWCI
- 6.92
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- Proceedings of the IEEE (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Electrostatic Discharge in Electronics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Integrated Circuits and Semiconductor Failure Analysis
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Keywords
- electrostatic discharge, integrated circuit reliability, ESD protection circuits, on-chip ESD protection, BiCMOS, CMOS process technology, ESD sensitivity
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review