Acceleration of FPGA based convolutional neural network for human activity classification using millimeter-wave radar
Open accessAbstract
Deep learning techniques have attracted much attention in the radar automatic target recognition. In this paper, we investigate an acceleration method of the convolutional neural network (CNN) on the field-programmable gate array (FPGA) for the embedded application of the millimeter-wave (mmW) radar-based human activity classification. Considering the micro-Doppler effect caused by a person's body movements, the spectrogram of mmW radar echoes is adopted as the CNN input. After that, according to the CNN architecture and the properties of the FPGA implementation, several parallel processing strategies are designed as well as data quantization and optimization of classification decision to accelerate the CNN execution. Finally, comparative experiments and discussions are carried out based on a measured dataset of nine individuals with four different actions by using a 77-GHz mmW radar. The results show that the proposed method not only maintains the high classification accuracy but also improves its execution speed, memory requirement, and power consumption. Specifically, compared with the implementation of the same network model on a graphics processing unit, it could achieve the speedup of about 30.42% at the cost of the classification accuracy loss of only 0.27%.
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In addition, interlayer parallel computing also can be viewed as a time series structure from the overall viewpoint of the CNN model.
“In addition, interlayer parallel computing also can be viewed as a time series structure from the overall viewpoint of the CNN model.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
In “Inter-Layer Parallel Computing,” the paper says the CNN model can be viewed as a time-series structure, not that interlayer parallel computing is one. It contrasts that sequential view with its parallel approach: a layer can begin before the previous layer finishes, allowing pipeline execution. (LLM, conf=0.84)
Checked by a reasoning model — may be wrong.
Experimental — accuracy not yet measuredPipelining is used as a technique for CNNrelated application as it computes all the functions in parallel.
“Pipelining is used as a technique for CNNrelated application as it computes all the functions in parallel.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The Inter-Layer Parallel Computing section says the CNN runs in a pipeline, starting some layer operations before the preceding layer finishes. It describes overlapping selected operations to reduce execution time, not computing all functions in parallel; page numbers are not available in the supplied copy. (LLM, conf=0.85)
Experimental — accuracy not yet measuredAll caches before the pooling are not required and the data cluster is transferred in parallel to save the time of operation in a single channel.
“All caches before the pooling are not required and the data cluster is transferred in parallel to save the time of operation in a single channel.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The “Convolution Group Parallel Computing” section says the cache before pooling may be unnecessary if data from a pooling region are provided in parallel, and describes optimizing caching and operation time within one channel. The claim overstates this conditional possibility as a categorical assertion that all such caches are unnecessary. (LLM, conf=0.88)
Experimental — accuracy not yet measuredThe entire CNN network and every convolution layer are accelerating on the Xilinx FPGA device.
“The entire CNN network and every convolution layer are accelerating on the Xilinx FPGA device.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
By implementing both interlayer and convolutional group parallelism in the overall network perspective, more efficient usage of caches can be achieved, where no cache is needed for max pooling layers.
“By implementing both interlayer and convolutional group parallelism in the overall network perspective, more efficient usage of caches can be achieved, where no cache is needed for max pooling layers.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The execution speed is improved in forward propagation through the network by the computation procedure of CNN and the pipelining technique on FPGA.
“The execution speed is improved in forward propagation through the network by the computation procedure of CNN and the pipelining technique on FPGA.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The removal of the softmax step could benefit the computation reduction, as when the dimensionality of the last fully connected layer output is 4 × 1, the classification decision can be optimized by the logic, which clearly benefits the FPGA that consists of a lot of logic gates.
“The removal of the softmax step could benefit the computation reduction, as when the dimensionality of the last fully connected layer output is 4 × 1, the classification decision can be optimized by the logic, which clearly benefits the FPGA that consists of a lot of logic gates [75].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The computational implementation included the channels and layers of the CNN with several parallel processing schemes that would reduce the waiting time and caching time indirectly and increase the speed of the network on FPGA.
“The computational implementation included the channels and layers of the CNN with several parallel processing schemes that would reduce the waiting time and caching time indirectly and increase the speed of the network on FPGA.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
In this application, the pipeline processing and multiple parallelism strategies show that there exists much runtime overlap between layers; thus, it is faster than the serial computing of the CNN execution.
“In this application, the pipeline processing and multiple parallelism strategies show that there exists much runtime overlap between layers; thus, it is faster than the serial computing of the CNN execution.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
The proposed method is validated with a variety of human activities measured using mmWradar data.
“The proposed method is validated with a variety of human activities measured using mmWradar data.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
When compared to the NVDIA GPU, the FPGA with the proposed acceleration method is 30.42% faster in the averaged execution time of CNN in test, and a 0.27% reduction in the classification accuracy is seen with 87.81%.
“When compared to the NVDIA GPU, the FPGA with the proposed acceleration method is 30.42% faster in the averaged execution time of CNN in test, and a 0.27% reduction in the classification accuracy is seen with 87.81% [75].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
There are various parallel processing strategies that are proposed for the data flow and computation patterns in the network model.
“There are various parallel processing strategies that are proposed for the data flow and computation patterns in the network model.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [75]
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- Authors
- Lei, P., Liang, J., Guan, Z., Wang, J., & Zheng, T.
- Affiliations
- Beihang University (CN)
- Venue
- IEEE Access
- Published
- 2019
- Volume
- 7
- Pages
- 88917-88926
- ISSN
- 2169-3536 (ISSN-L)
- OpenAlex
- W2953554277
- Cited by
- 44
- References
- 25
- Citations by year
- 2026: 3 · 2025: 5 · 2024: 7 · 2023: 9 · 2022: 3 · 2021: 10 · 2020: 5 · 2019: 2
- FWCI
- 5.09
- Type
- journal article
- Language
- en
- Open access
- gold
- doi.org
- Locations
- IEEE Access (publishedVersion, cc-by)
- DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion, cc-by-sa)
- Funders
- National Natural Science Foundation of China (61501011, 61671035)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Engineering › Aerospace Engineering › Advanced SAR Imaging Techniques
- Keywords
- FPGA acceleration, convolutional neural networks, human activity classification, millimeter-wave radar, micro-Doppler spectrogram, parallel computing, data quantization, 77 GHz radar, embedded hardware, power consumption, automatic target recognition
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