The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.
A low-noise self-calibrating dynamic comparator for high-speed ADCs
Abstract
This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 μW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.
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Cites
Principles of Data Conversion System Design
Razavi, B. (1994) · Institute of Electrical and Electronics Engineers eBooks · doi:10.1109/9780470545638 · Cited by 946
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
Schinkel, D., Mensink, E., Klumperink, E. A. M., van Tuijl, E., & Nauta, B. (2007) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2007.373420 · Cited by 746
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process
Van der Plas, G., Decoutere, S., & Donnay, S. (2006) · 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers · doi:10.1109/isscc.2006.1696294 · Cited by 229
Cited by
Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Brandli, M., Kossel, M., Morf, T., Andersen, T. M., & Leblebici, Y. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2279571 · Cited by 347
Correll, J. M., Bothra, V., Cai, F., Lim, Y., Lee, S. H., Lee, S., Lu, W. D., Zhang, Z., & Flynn, M. P. (2020) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2020.2992228 · Cited by 36
Metadata
- Authors
- Miyahara, M., Asada, Y., Paik, D., & Matsuzawa, A.
- Venue
- 2008 IEEE Asian Solid-State Circuits Conference
- Publisher
- IEEE
- Published
- 2008-11
- Pages
- 269-272
- OpenAlex
- W2172010302
- Cited by
- 420
- References
- 3
- FWCI
- 24.72
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Miyahara, M., Asada, Y., Paik, D., & Matsuzawa, A. (2008). A low-noise self-calibrating dynamic comparator for high-speed ADCs. 2008 IEEE Asian Solid-State Circuits Conference. https://doi.org/10.1109/asscc.2008.4708780
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