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Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
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Transformers have transformed the field of natural language processing. Their superior performance is largely attributed to the use of stacked “self-attention” layers, each of which consists of matrix multiplies as well as softmax operations. As a result, unlike other neural networks, the softmax operation accounts for a significant fraction of the total run-time of Transformers. To address this, we propose Softermax, a hardware-friendly softmax design. Softermax consists of base replacement, low-precision softmax computations, and an online normalization calculation. We show Softermax results in 2.35x the energy efficiency at 0.90x the size of a comparable baseline, with negligible impact on network accuracy.
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![Fig. 4 (a) The Unnormed Softmax Unit determines the local max, performs the power of 2 calculation using the current max, and accumulates the denominator. (b) The Normalization Unit performs the renormalization of the numerator, as well as the final division of the numerator by the accumulated sum. (c) In an example accelerator [17], the Unnormed Softmax can be integrated into the post-processing vector unit on a per PE basis, while the Normalization Unit can be shared across multiple PEs and integrated between the PEs and the Global Buffer](/paper-figures/46f03c2ffabd423f83b1ca0c67587f1a/softermax-hardware-software-co-design-of-an-efficient-softmax-for-transformers-figure-4.png)
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“Non-linear operations like Softmax, LayerNorm, and GELU, though less prevalent, present computational challenges on conventional hardware due to their complexity, potentially restricting the enhancement of end-to-end transformer inference [31].”
From Model Quantization and Hardware Acceleration for Vision Transformers: A Comprehensive Survey (2024) · cites this paper as [31]
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“A large portion of the inference time in ViT models is consumed by floating-point non-linear activations, normalizations, and the associated quantization and dequantization operations [31].”
From Model Quantization and Hardware Acceleration for Vision Transformers: A Comprehensive Survey (2024) · cites this paper as [31]
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“In addition, various approximation methods that hold floating-point arithmetic are presented [36, 50]; while they lower certain computational costs, they cannot meet the demands of integer arithmetic.”
From I-ViT: Integer-only Quantization for Efficient Vision Transformer Inference (2023) · cites this paper as [36]
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“Due to the non-linearity, Softmax cannot follow the dyadic arithmetic pipeline discussed above, and the exponential arithmetic in Eq. 11 is typically unsupported by integer-only logic units [36].”
From I-ViT: Integer-only Quantization for Efficient Vision Transformer Inference (2023) · cites this paper as [36]
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Wang, Z., Fan, H., Waris, H., Wang, G., Li, Z., Jiang, J., Sun, Y., & He, G. (2025) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac63849.2025.11132861 · Cited by 2
MATA: A Memory-Efficient Attention Accelerator for LLMs Exploiting Look-Back KV Cache Pruning
Zhu, Z., Li, G., Liu, T., Mo, Z., Liang, X., & Cheng, J. (2025) · IEEE Transactions on Computers · doi:10.1109/tc.2025.3626150 · Cited by 2
Ahmed, S., Li, J., Zhuang, W., Chen, C., & Lyu, L. (2025) · IEEE/CVF International Conference on Computer Vision (ICCV) · doi:10.1109/iccv51701.2025.01968 · Cited by 2
NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator
Upadhyay, M., Juneja, R., Wong, W., & Peh, L.-S. (2024) · Design, Automation, and Test in Europe · doi:10.23919/date58400.2024.10546727 · Cited by 4
An Energy-Efficient Architecture of Approximate Softmax Functions for Transformer in Edge Computing
Li, S., Yin, B., & Zhang, H. (2023) · International Conference on Electronics and Electrical Engineering Technology (EEET) · doi:10.1109/eeet61723.2023.00015 · Cited by 3
Vision Transformer Inference on a CNN Accelerator
Yi, C., Moh, H., & Ha, S. (2024) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd63220.2024.00101 · Cited by 3
Serving Transformer Models via Joint Requst Scheduling and Batching in the Network Edge
Fu, B., Chen, F., Li, P., & Zeng, D. (2025) · IEEE Transactions on Sustainable Computing · doi:10.1109/tsusc.2025.3528105 · Cited by 3
An Efficient Training Architecture for Nonlinear Softmax Function in Transformers
Shao, H., & Wang, Z. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11044130 · Cited by 2
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators
Alexandridis, K., Titopoulos, V., & Dimitrakopoulos, G. (2025) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi65124.2025.11130263 · Cited by 6
Colagrande, L., & Luca Benini, C. (2025) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac63849.2025.11132520 · Cited by 2
Hun, R., Xu, J., Sun, M., Zhang, S., Chen, Y., & Chiang, P. Y. (2022) · International Conference on Communications, Circuits and Systems · doi:10.1109/icccas55266.2022.9825471 · Cited by 2
APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning
Sun, Q., Meng, R., Fan, H., Ding, F., Lu, L., Wu, J., Li, X., & Yan, G. (2025) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3658617.3697655 · Cited by 1
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Asynchronous Design of a Bitwise Elimination Argmax via High-Level Modeling in GraphRack
Squires-Parkin, H., Chan, A., Shafik, R., Wheeldon, A., & Yakovlev, A. (2025) · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · doi:10.1109/async65240.2025.00021 · Cited by 1
Heo, J., Rho, S., Kim, K., & Chung, K.-S. (2025) · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · doi:10.1109/coolchips65488.2025.11018597 · Cited by 1
An Integer-only Quantization Framework for Edge Deployment of Large Language Models
Hu, Y., Yuan, Z., Gao, W., Zhang, S., & Liu, Y. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043993 · Cited by 1
TEA-SPS: A Tiny and Efficient Architecture for Softmax With Parallelism and Sparsity Adaptability
Cui, Z., Ma, Y., Cheng, Y., Mei, Z., Yan, F., Pan, H., & Wang, Y. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3610210 · Cited by 1
Hardware-Oriented and Precisely Approximated Online Softmax for Deep Learning Models
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Sparse Approximation of Softmax: Hardware-Efficient Acceleration for Long Sequence Inference
Ma, L., Zhao, Z., Wu, X., Chen, G. P., & Yin, W. (2025) · IEEE International Conference on ASIC (ASICON) · doi:10.1109/asicon66040.2025.11326470 · Cited by 1
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Vectorized FlashAttention with low-cost exponential computation in RISC-V vector processors
Titopoulos, V., Alexandridis, K., & Dimitrakopoulos, G. (2026) · The Journal of Supercomputing · doi:10.1007/s11227-026-08322-x · Cited by 1
ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers
Yang, J., Tombesi, G., Zuckerman, J., & Carloni, L. P. (2025) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl68686.2025.00014 · Cited by 1
Hardware-Efficient Softmax and Layer Normalization with Guaranteed Normalization for Edge Devices
Choi, D., Kim, H., & Kim, J. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562304 · Cited by 1
Activation Function Integration for Accelerating Multi-Layer Graph Convolutional Neural Networks
Grailoo, M., Nikoubin, T., Gustafsson, O., & Nunez-Yanez, J. L. (2024) · IEEE Dallas Circuits and Systems Conference (DCAS) · doi:10.1109/dcas61159.2024.10539892 · Cited by 1
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Meng, Z., Shu, L., Zeng, J., Li, Z., Lv, K., Yang, H., & Hao, J. (2024) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2024.3488782 · Cited by 1
Metadata
- Authors
- Stevens, J. R., Venkatesan, R., Dai, S., Khailany, B., & Raghunathan, A.
- Affiliations
- Purdue University West Lafayette (US)
- Nvidia (United Kingdom) (GB)
- Venue
- 2021 58th ACM/IEEE Design Automation Conference (DAC)
- Publisher
- IEEE
- Published
- 2021-12-05
- Pages
- 469-474
- ISSN
- 0738-100X (ISSN-L)
- OpenAlex
- W3137649401
- Cited by
- 148
- References
- 23
- Citations by year
- 2026: 22 · 2025: 68 · 2024: 35 · 2023: 16 · 2022: 5 · 2021: 2
- FWCI
- 4.74
- Type
- conference paper
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- ACM/IEEE Design Automation Conference (DAC) (publishedVersion)
- arXiv (Cornell University) (submittedVersion, cc-by-nc-nd)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- softmax, transformer models, hardware-software co-design, self-attention, low-precision arithmetic, energy efficiency, neural network acceleration
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
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