CoChat
Sign Up
Cited by 340Advanced Memory and Neural ComputingParallel Computing and Optimization TechniquesLow-power high-performance VLSI design

The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.

Overcoming the challenges of crossbar resistive memory architectures

Xu, Cong, Niu, Dimin, Muralimanohar, Naveen, Balasubramonian, Rajeev, Zhang, Tao, Yu, Shimeng, Xie, Yuan·2015·2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
DOI 10.1109/hpca.2015.7056056
Open this paper in CoChat — free account

Abstract

The scalability of DRAM faces challenges from increasing power consumption and the difficulty of building high aspect ratio capacitors. Consequently, emerging memory technologies including Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM), and Resistive RAM (ReRAM) are being actively pursued as replacements for DRAM memory. Among these candidates, ReRAM has superior characteristics such as high density, low write energy, and high endurance, making it a very attractive cost-efficient alternative to DRAM. In this paper, we present a comprehensive study of ReRAM-based memory systems. ReRAM's high density comes from its unique crossbar architecture where some peripheral circuits are laid below multiple layers of ReRAM cells. A crossbar architecture introduces special constraints on operating voltages, write latency, and array size. The access latency of a crossbar is a function of the data patterns involved in a write operation. These combined with ReRAM's exponential relationship between its write voltage and switching latency provide opportunities for architectural optimizations. This paper makes several key contributions. First, we study the crossbar architecture and describe trade-offs involving voltage drop, write latency, and data pattern. We then analyze microarchitectural enhancements such as double-sided ground biasing and multiphase reset operations to improve write performance. At the architecture level, a simple compression based data encoding scheme is pr…

Overview

Integrity signals

Registry

Crossref · 10.1109/hpca.2015.7056056

Cites

1 of 1 references verified0 citation errors · 0 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Verification

Claims the paper makes

This paper’s full text isn’t openly available, so its claims and self-check weren’t run. The registry and citation checks still apply.

Citations

Cites

Flagged first, then by citations

Research works printed but not linked: 56

  1. 10.1145/1815961.1815980 · DOI
  2. 10.1109/MC.2011.18 · DOI
  3. qureshi, 2012, PreSET: Improving Performance of Phase Change Memories by Exploiting Asymmetry in Write Times, Proceedings of the International Symposium on omputer Architecture (ISCA), 380, 10.1145/2366231.2337203 · DOI
  4. 10.1109/ISVLSI.2012.82 · DOI
  5. 10.1145/2370816.2370870 · DOI
  6. 10.1145/2370816.2370911 · DOI
  7. 10.1145/1555754.1555760 · DOI
  8. 10.1145/1669112.1669117 · DOI
  9. 10.1145/2155620.2155658 · DOI
  10. 10.1109/HPCA.2010.5416645 · DOI
  11. 0, Micron DDR3 SDRAM Data Sheet
  12. 0, TN-41-01 Calculating Memory System Power for DDR 3
  13. 10.1145/2333660.2333712 · DOI
  14. 10.1145/2024716.2024718 · DOI · Paper page
  15. 10.1145/2485922.2485961 · DOI
  16. lee, 2010, Evidence and Solution of Over-RESET problem for HfOX Based Resistive Memory with Sub-ns Switching Speed and High Endurance, Proceedings of the IEEE International Electron Devices Meeting (IEDM), 19.7.1
  17. 10.1038/nmat3070 · DOI · Paper page
  18. liu, 2012, RAIDR: Retention-aware Intelligent DRAM Refresh, Proceedings of the International Symposium on Computer Architecture (ISCA), 1, 10.1145/2366231.2337161 · DOI
  19. 0, ModelSim
  20. mccalpin, 0, Stream Benchmark
  21. 10.1109/HPCA.2014.6835933 · DOI
  22. 10.1109/JPROC.2012.2190369 · DOI · Paper page
  23. 10.1145/1687399.1687448 · DOI
  24. 10.1145/1555754.1555759 · DOI
  25. 10.1109/HPCA.2014.6835947 · DOI
  26. yue, 2013, Accelerating Write by Exploiting PCM Asymmetries, IEEE International Symposium on High Performance Computer Architecture (HPCA), 282
  27. 10.1109/LED.2010.2078794 · DOI
  28. 10.1109/HPCA.2011.5749752 · DOI
  29. xu, 2011, Design Implications of Memristor-Based RRAM Cross-Point Structures, Design Automation Test in Europe Conference Exhibition (DATE), 1
  30. govoreanu, 2011, 10x 10nm2 Hf/HfOx Cross-point Resistive RAM with Excellent Performance, Reliability and Low-Energy Operation, Proceedings of the IEEE International Electron Devices Meeting (IEDM), 31.6.1
  31. 10.1145/2155620.2155642 · DOI
  32. 10.1145/1815961.1816014 · DOI
  33. henning, 2007, Performance Counters and Development of SPEC CPU2006, SIGARCH Comput Archit News, 35, 118, 10.1145/1241601.1241623 · DOI
  34. 0, The Memristor Project
  35. 10.1145/1736020.1736023 · DOI
  36. 0, International Technology Roadmap for Semiconductors
  37. 10.1109/HPCA.2013.6522321 · DOI
  38. 10.1109/HPCA.2012.6169027 · DOI
  39. 10.1109/ISSCC.2012.6177078 · DOI
  40. 10.1145/1555754.1555758 · DOI
  41. 10.1109/VLSIT.2012.6242451 · DOI
  42. 10.1116/1.3301579 · DOI
  43. 10.1109/ISSCC.2012.6176872 · DOI
  44. 10.1145/1669112.1669157 · DOI
  45. 10.1145/2485922.2485959 · DOI
  46. 10.1145/1629575.1629589 · DOI
  47. 10.1145/1815961.1815983 · DOI
  48. 10.1109/ISSCC.2014.6757460 · DOI
  49. 10.1109/HPCA.2009.4798259 · DOI
  50. 10.1109/MICRO.2010.22 · DOI
  51. 0, Design Compiler
  52. 10.1145/2155620.2155659 · DOI
  53. 10.1145/2485922.2485960 · DOI
  54. 10.1109/MICRO.2010.46 · DOI
  55. 10.1109/HPCA.2011.5749716 · DOI
  56. 10.1109/HPCA.2014.6835972 · DOI

Cited by

Sorted by citations

Metadata

Authors
Xu, C., Niu, D., Muralimanohar, N., Balasubramonian, R., Zhang, T., Yu, S., & Xie, Y.
Affiliations
  • Pennsylvania State University (US)
  • Hewlett-Packard (United States) (US)
  • Arizona State University (US)
ORCID
Venue
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
Publisher
IEEE
Published
2015-02
Pages
476-488
ISSN
1530-0897 (ISSN-L)
DOI
10.1109/hpca.2015.7056056
OpenAlex
W2013028205
Cited by
340
References
1
Citations by year
2026: 12 · 2025: 14 · 2024: 9 · 2023: 31 · 2022: 23 · 2021: 39 · 2020: 34 · 2019: 57 · 2018: 52 · 2017: 27 · 2016: 33 · 2015: 9
FWCI
49.96
Type
conference paper
Language
en
Open access
closed
Locations
  • IEEE International Symposium on High-Performance Computer Architecture (HPCA) (publishedVersion)
  • Rare & Special e-Zone (The Hong Kong University of Science and Technology) (submittedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords
resistive random access memory, crossbar architecture, memory architecture, write latency, voltage drop, data encoding, DRAM replacement, main memory, phase-change memory, STT-MRAM

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review