The DOI matches its Crossref record; 35 of the 36 references it cites were found in a registry or an index.
An Overview of FPGA Based Deep Learning Accelerators: Challenges and Opportunities
Abstract
With the rapid development of in-depth learning, neural network and deep learning algorithms have been widely used in various fields, e.g., image, video and voice processing. However, the neural network model is getting larger and larger, which is expressed in the calculation of model parameters. Although a wealth of existing efforts on GPU platforms currently used by researchers for improving computing performance, dedicated hardware solutions are essential and emerging to provide advantages over pure software solutions. In this paper, we systematically investigate the neural network accelerator based on Field-Programmable Gate Array(FPGA). Specifically, we respectively review the accelerators designed for specific problems, specific algorithms, algorithm features, and general templates. We also compared the design and implementation of the accelerator based on FPGA under different devices and network models and compared it with the versions of CPU and GPU. Finally, we present to discuss the advantages and disadvantages of accelerators on FPGA platforms and to further explore the opportunities for future research.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
In the citing paper
“it requires a lot of time in reconfiguration.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [88]
In the citing paper
“Although it brings a lot of advantages on flexibility and high parallelism [88]”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [88]
In the citing paper
“In addition, challenges in programming are another increase in cost [88].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [88]
Citations
Cites
Deep Residual Learning for Image Recognition
He, K., Zhang, X., Ren, S., & Sun, J. (2016) · 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2016.90 · Cited by 235,474
Very Deep Convolutional Networks for Large-Scale Image Recognition
Simonyan, K., & Zisserman, A. (2014) · arXiv · doi:10.48550/arxiv.1409.1556 · Cited by 114,148
A fast learning algorithm for deep belief nets
Hinton, G. E., Osindero, S., & Teh, Y.-W. (2006) · Neural Computation · doi:10.1162/neco.2006.18.7.1527 · Cited by 16,336
Han, S., Mao, H., & Dally, W. J. (2015) · arXiv · doi:10.48550/arxiv.1510.00149 · Cited by 4,662
Recurrent Neural Network RegularizationPreprint
Zaremba, W., Sutskever, I., & Vinyals, O. (2014) · arXiv (Cornell University) · doi:10.48550/arxiv.1409.2329 · Cited by 3,233
Williams, S., Waterman, A., & Patterson, D. A. (2009) · Communications of the ACM · doi:10.1145/1498765.1498785 · Cited by 2,798
Convolutional networks and applications in vision
LeCun, Y., Kavukcuoglu, K., & Farabet, C. (2010) · Proceedings of 2010 IEEE International Symposium on Circuits and Systems · doi:10.1109/iscas.2010.5537907 · Cited by 2,213
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
Zhou, S., Wu, Y., Ni, Z., Zhou, X., Wen, H., & Zou, Y. (2016) · arXiv · doi:10.48550/arxiv.1606.06160 · Cited by 1,690
Self-citationGoing Deeper with Embedded FPGA Platform for Convolutional Neural Network
Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., et al. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847265 · Cited by 1,290
Research works printed but not linked: 2
- ma, 2017, End-toend scalable fpga accelerator for deep residual networks, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1
- qinrang, 2018, Calculation optimization for convolutional neural networks and fpga-based accelerator design using the parameters sparsity, Journal of Electronics & Information Technology, 40, 1368
Cited by
Computer vision algorithms and hardware implementations: A survey
Feng, X., Jiang, Y., Yang, X., Du, M., & Li, X. S. (2019) · Integration · doi:10.1016/j.vlsi.2019.07.005 · Cited by 381
A Survey on Edge Computing Systems and Tools
Liu, F., Tang, G., Li, Y., Cai, Z., Zhang, X., & Zhou, T. (2019) · Proceedings of the IEEE · doi:10.1109/jproc.2019.2920341 · Cited by 361
A Machine Learning-Oriented Survey on Tiny Machine Learning
Capogrosso, L., Cunico, F., Cheng, D. S., Fummi, F., & Cristani, M. (2024) · IEEE Access · doi:10.1109/access.2024.3365349 · Cited by 214
Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey
Pudi, D., Boppu, S., Manikandan, M. S., & Cenkeramaddi, L. R. (2022) · IEEE Access · doi:10.1109/access.2022.3229767 · Cited by 155
Semantics for Robotic Mapping, Perception and Interaction: A Survey
Garg, S., Sünderhauf, N., Dayoub, F., Morrison, D., Cosgun, A., Carneiro, G., Wu, Q., Chin, T.-J., Reid, I. D., Gould, S. J., et al. (2020) · Foundations and Trends in Robotics · doi:10.1561/2300000059 · Cited by 124
Metadata
- Authors
- Wang, T., Wang, C., Zhou, X., & Chen, H.
- Affiliations
- University of Science and Technology of China (CN)
- Venue
- 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)
- Publisher
- IEEE
- Published
- 2019-08
- Pages
- 1674-1681
- OpenAlex
- W2977485436
- Cited by
- 53
- References
- 36
- Citations by year
- 2026: 4 · 2025: 8 · 2024: 5 · 2023: 13 · 2022: 5 · 2021: 8 · 2020: 6 · 2019: 4
- FWCI
- 4.53
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE International Conference on High Performance Computing and Communications; IEEE International Conference on Smart City; IEEE International Conference on Data Science and Systems (HPCC/SmartCity/DSS) (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- FPGA, deep learning accelerators, neural network hardware, hardware acceleration, model parameter size
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
Data sources
Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
