The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Abstract
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
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Cites
Review on high-k dielectrics reliability issues
Ribes, G., Mitard, J., Denais, M., Bruyere, S., Monsieur, F., Parthasarathy, C., Vincent, E., & Ghibaudo, G. (2005) · IEEE Transactions on Device and Materials Reliability · doi:10.1109/tdmr.2005.845236 · Cited by 533
Cited by
Qubits made by advanced semiconductor manufacturing
Zwerver, A. M. J., Krähenmann, T., Watson, T. F., Lampert, L., George, H. C., Pillarisetty, R., Bojarski, S. A., Amin, P., Amitonov, S. V., Boter, J. M., et al. (2022) · Nature Electronics · doi:10.1038/s41928-022-00727-9 · Cited by 364
CMOS Scaling Trends and Beyond
Bohr, M. T., & Young, I. A. (2017) · IEEE Micro · doi:10.1109/mm.2017.4241347 · Cited by 336
Mathew, S. K., Srinivasan, S., Anders, M. A., Kaul, H., Hsu, S. K., Sheikh, F., Agarwal, A., Satpathy, S., & Krishnamurthy, R. K. (2012) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2012.2217631 · Cited by 195
Metadata
- Authors
- Mistry, K., Chau, R., Choi, C.-H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Allen, C., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Auth, C., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Beattie, B., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Bergstrom, D., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K., Bost, M., Brazier, M., Buehler, M., & Cappellani, A.
- Venue
- 2007 IEEE International Electron Devices Meeting
- Publisher
- IEEE
- Published
- 2007-12
- Pages
- 247-250
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2001894083
- Cited by
- 854
- References
- 1
- FWCI
- 104.19
- Type
- conference paper
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. https://app.cochat.ai/papers/10.1109/iedm.2007.4418914
- The paper
- Mistry, K., Chau, R., Choi, C.-H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Allen, C., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., . . . Cappellani, A. (2007). A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. 2007 IEEE International Electron Devices Meeting. https://doi.org/10.1109/iedm.2007.4418914
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
