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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
Abstract
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4thgeneration high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.
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Citations
Cited by
CMOS Scaling Trends and Beyond
Bohr, M. T., & Young, I. A. (2017) · IEEE Micro · doi:10.1109/mm.2017.4241347 · Cited by 336
Science and research policy at the end of Moore’s law
Khan, H. N., Hounshell, D. A., & Fuchs, E. R. H. (2018) · Nature Electronics · doi:10.1038/s41928-017-0005-9 · Cited by 319
Mathew, S. K., Johnston, D., Satpathy, S., Suresh, V., Newman, P., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S. K., Chen, G., et al. (2016) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2558490 · Cited by 102
Metadata
- Authors
- Natarajan, S., Agostinelli, M., Akbar, S., Bost, M., Bowonder, A., Chikarmane, V., Chouksey, S., Dasgupta, A., Fischer, K., Fu, Q., Ghani, T., Giles, M., Govindaraju, S., Grover, R., Han, W., Hanken, D., Haralson, E., Haran, M., Heckscher, M., Heussner, R., Jain, P., James, R., Jhaveri, R., Jin, I., Kam, H., Karl, E., Kenyon, C., Liu, M., Luo, Y., Mehandru, R., Morarka, S., Neiberg, L., Packan, P., Paliwal, A., Parker, C., Patel, P., Patel, R., Pelto, C., Pipes, L., Plekhanov, P., Prince, M., Rajamani, S., Sandford, J., Sell, B., Sivakumar, S., Smith, P., Song, B., Tone, K., Troeger, T., Wiedemer, J., Yang, M., & Zhang, K.
- Venue
- 2014 IEEE International Electron Devices Meeting
- Publisher
- IEEE
- Published
- 2014-12
- Pages
- 3.7.1-3.7.3
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W1966797259
- Cited by
- 543
- References
- 0
- FWCI
- 87.77
- Type
- conference paper
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size. https://app.cochat.ai/papers/10.1109/iedm.2014.7046976
- The paper
- Natarajan, S., Agostinelli, M., Akbar, S., Bost, M., Bowonder, A., Chikarmane, V., Chouksey, S., Dasgupta, A., Fischer, K., Fu, Q., Ghani, T., Giles, M., Govindaraju, S., Grover, R., Han, W., Hanken, D., Haralson, E., Haran, M., Heckscher, M., . . . Zhang, K. (2014). A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size. 2014 IEEE International Electron Devices Meeting. https://doi.org/10.1109/iedm.2014.7046976
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
