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A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
Abstract
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5thgeneration high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology.
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Metadata
- Authors
- Auth, C., Aliyarukunju, A., Asoro, M., Bergstrom, D., Bhagwat, V., Birdsall, J., Bisnik, N., Buehler, M., Chikarmane, V., Ding, G., Fu, Q., Gomez, H., Han, W., Hanken, D., Haran, M., Hattendorf, M., Heussner, R., Hiramatsu, H., Ho, B., Jaloviar, S., Jin, I., Joshi, S., Kirby, S., Kosaraju, S., Kothari, H., Leatherman, G., Lee, K., Leib, J., Madhavan, A., Marla, K., Meyer, H., Mule, T., Parker, C., Parthasarathy, S., Pelto, C., Pipes, L., Post, I., Prince, M., Rahman, A., Rajamani, S., Saha, A., Santos, J. D., Sharma, M., Sharma, V., Shin, J., Sinha, P., Smith, P., Sprinkle, M., Amour, A. S., Staus, C., Suri, R., Towner, D., Tripathi, A., Tura, A., Ward, C., & Yeoh, A.
- Venue
- 2017 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2017-12
- Pages
- 29.1.1-29.1.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2787310733
- Cited by
- 384
- References
- 0
- FWCI
- 60.71
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Auth, C., Aliyarukunju, A., Asoro, M., Bergstrom, D., Bhagwat, V., Birdsall, J., Bisnik, N., Buehler, M., Chikarmane, V., Ding, G., Fu, Q., Gomez, H., Han, W., Hanken, D., Haran, M., Hattendorf, M., Heussner, R., Hiramatsu, H., Ho, B., . . . Yeoh, A. (2017). A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects. 2017 IEEE International Electron Devices Meeting (IEDM). https://doi.org/10.1109/iedm.2017.8268472
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
