The DOI matches its Crossref record; 45 of the 45 references it cites were found in a registry or an index.
Memory scaling: A systems architecture perspective
Open accessAbstract
The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques. In this paper, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we survey three key solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system, 2) designing a memory system that employs emerging memory technologies and takes advantage of multiple different technologies, 3) providing predictable performance and QoS to applications sharing the memory system. We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.
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Cites
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Architecting phase change memory as a scalable dram alternative
Lee, B. C., İpek, E., Mutlu, O., & Burger, D. (2009) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/1555754.1555758 · Cited by 1,380
Self-citationScalable high performance main memory system using phase-change memory technology
Qureshi, M. K., Srinivasan, V., & Rivers, J. A. (2009) · Proceedings of the 36th annual international symposium on Computer architecture · doi:10.1145/1555754.1555760 · Cited by 1,277
Phase-change random access memory: A scalable technology
Raoux, S., Burr, G. W., Breitwisch, M. J., Rettner, C. T., Chen, Y.-C., Shelby, R. M., Salinga, M., Krebs, D., Chen, S.-H., Lung, H.-L., et al. (2008) · IBM Journal of Research and Development · doi:10.1147/rd.524.0465 · Cited by 1,010
Better I/O through byte-addressable, persistent memory
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Personalized copy number and segmental duplication maps using next-generation sequencing
Alkan, C., Kidd, J. M., Marques-Bonet, T., Aksay, G., Antonacci, F., Hormozdiari, F., Kitzman, J. O., Baker, C., Malig, M., Mutlu, O., et al. (2009) · Nature Genetics · doi:10.1038/ng.437 · Cited by 748
Self-citation3D-Stacked Memory Architectures for Multi-core Processors
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Cited by
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
Kim, Y., Daly, R., Kim, J., Fallin, C., Lee, J. H., Lee, D., Wilkerson, C., Lai, K., & Mutlu, O. (2014) · 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2014.6853210 · Cited by 465
Self-citationScaling for edge inference of deep neural networks
Xu, X., Ding, Y., Hu, S. X., Niemier, M., Cong, J., Hu, Y., & Shi, Y. (2018) · Nature Electronics · doi:10.1038/s41928-018-0059-3 · Cited by 462
Processing data where it makes sense: Enabling in-memory computation
Mutlu, O., Ghose, S., Gómez-Luna, J., & Ausavarungnirun, R. (2019) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2019.01.009 · Cited by 300
Self-citationData retention in MLC NAND flash memory: Characterization, optimization, and recovery
Cai, Y., Luo, Y., Haratsch, E. F., Mai, K., & Mutlu, O. (2015) · 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2015.7056062 · Cited by 274
Self-citationBrain-inspired computing systems: a systematic literature review
Zolfagharinejad, M., Alegre-Ibarra, U., Chen, T., Kinge, S., & van der Wiel, W. G. (2024) · The European Physical Journal B · doi:10.1140/epjb/s10051-024-00703-6 · Cited by 39
“Transistors in arithmetic logic units and memory circuits have both gone through this miniaturization, yet at different rates [18] (purple vs. blue curve in Fig.”
Background
Metadata
- Authors
- Mutlu, O.
- Venue
- 2013 5th IEEE International Memory Workshop
- Publisher
- IEEE
- Published
- 2013-05
- Pages
- 21-25
- OpenAlex
- W2135965542
- Cited by
- 256
- References
- 45
- FWCI
- 10.17
- Type
- conference paper
- Language
- en
- Open access
- green
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