Lattice Boltzmann simulation optimization on leading multicore platforms
Open accessAbstract
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of search-based performance optimizations, popular in linear algebra and FFT libraries, to application-specific computational kernels. Our work applies this strategy to a lattice Boltzmann application (LBMHD) that historically has made poor use of scalar microprocessors due to its complex data structures and memory access patterns. We explore one of the broadest sets of multicore architectures in the HPC literature, including the Intel Clovertown, AMD Opteron X2, Sun Niagara!, STI Cell, as well as the single core Intel Itanium.2. Rather than hand-tuning LBMHD for each system, we develop a code generator that allows us identify a highly optimized version for each platform, while amortizing the human programming effort. Results show that our auto- tuned LBMHD application achieves up to a 14times improvement compared with the original code. Additionally, we present detailed analysis of each optimization, which reveal surprising hardware bottlenecks and software challenges for future multicore systems and applications.
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Directed automated testing (concolic unit testing) has shown promise for improving software quality through automated test generation using static and dynamic analyses.
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From A view of the parallel computing landscape (2009) · cites this paper as [21]
Section 2.2 describes a code generator for auto-tuning lattice Boltzmann simulations, and Section 6 discusses performance optimizations. Neither addresses concolic unit testing, software-quality improvements, or test generation using static and dynamic analyses; searches for those terms returned no relevant passage. Page numbers were not available in our copy. (LLM, conf=0.78)
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Self-citation
- Authors
- Williams, S., Carter, J., Oliker, L., Shalf, J., & Yelick, K.
- Affiliations
- Lawrence Berkeley National Laboratory (US)
- Corresponding author
- Williams, Samuel
- Venue
- 2008 IEEE International Symposium on Parallel and Distributed Processing
- Publisher
- IEEE
- Published
- 2008-04
- Pages
- 1-14
- ISSN
- 1530-2075 (ISSN-L)
- OpenAlex
- W254119393
- Cited by
- 98
- References
- 17
- Citations by year
- 2024: 2 · 2023: 1 · 2022: 2 · 2021: 3 · 2020: 3 · 2019: 2 · 2018: 1 · 2017: 3 · 2016: 2 · 2015: 5 · 2014: 3 · 2013: 2 · 2012: 11
- FWCI
- 11.38
- Type
- conference paper
- Language
- en
- Open access
- green
- escholarship.org
- Locations
- IEEE International Parallel and Distributed Processing Symposium (IPDPS) (publishedVersion)
- eScholarship (California Digital Library) (submittedVersion)
- OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) (submittedVersion)
- University of North Texas Digital Library (University of North Texas) (submittedVersion)
- Funders
- U.S. Department of Energy (-AC02-05CH11231, 05CH11231, DE AC02 05CH11231, DE-AC02-)
- Forschungszentrum Jülich
- Office of Science (DEAC02–05CH11231, AC02-05CH11231, DE-AC02, 05CH11231)
- National Institute on Aging
- Advanced Scientific Computing Research (DE-AC02-05CH11231, AC02-05CH11231)
- Lawrence Berkeley National Laboratory (AC02‐05CH11231, DE-AC02-05CH11231, 05CH11231)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Engineering › Computational Mechanics › Lattice Boltzmann Simulation Studies
- Physical Sciences › Computer Science › Computer Graphics and Computer-Aided Design › Computer Graphics and Visualization Techniques
- Keywords
- lattice Boltzmann method, auto-tuning, multi-core processors, performance optimization, code generation, search-based optimization, memory access patterns, hardware bottlenecks, Cell processor, AMD Opteron
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