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Current balancing control for parallel connected IGBTs using programmable gate driver output resistance
Abstract
A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Routto minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Routis implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMC's 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.
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In the citing paper
“The dynamic R G control is presented and implemented in [52,53] for parallel-connected IGBTs to realize dynamic V GE adjustment.”
From Paralleling of IGBT Power Semiconductor Devices and Reliability Issues (2023) · cites this paper as [53]
In the citing paper
“Furthermore, turn-on and turn-off delay time parameters can also be controlled by dynamic resistance control.”
From Paralleling of IGBT Power Semiconductor Devices and Reliability Issues (2023) · cites this paper as [53]
In the citing paper
“The dynamic adjustment of V GE can be realized through dynamic R G control.”
From Paralleling of IGBT Power Semiconductor Devices and Reliability Issues (2023) · cites this paper as [53]
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No references could be resolved yet.
Research works printed but not linked: 8
- 10.1109/PESC.1996.548751 · DOI · Paper page
- 10.1109/ISPSD.1998.702645 · DOI
- 10.1109/ECCE.2011.6064173 · DOI · Paper page
- 10.1109/ICIT.2010.5472617 · DOI · Paper page
- 10.1109/TPS.2008.2003971 · DOI · Paper page
- 10.1109/63.761687 · DOI
- 10.1109/ISPSD.2011.5890866 · DOI
- 10.1109/APEC.2013.6520216 · DOI · Paper page
Cited by
Paralleling of IGBT Power Semiconductor Devices and Reliability Issues
Tripathi, R. N., & Omura, I. (2023) · Electronics · doi:10.3390/electronics12183826 · Cited by 14
An Effective Current Balancing Method for Inverters With Paralleled Silicon Carbide Power Modules
Lin, N., Zhao, Y., & Mantooth, H. A. (2023) · IEEE Transactions on Industry Applications · doi:10.1109/tia.2023.3306750 · Cited by 13
Metadata
- Authors
- Sasaki, M., Nishio, H., Shorten, A., & Ng, W. T.
- Venue
- 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)
- Publisher
- IEEE
- Published
- 2013-05
- Pages
- 65-68
- Cited by
- 24
- References
- 0
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
