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An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
Abstract
Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.
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Cited by
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2010.2042254 · Cited by 1,329
Fan, Q., Sebastiano, F., Huijsing, J. H., & Makinwa, K. A. A. (2011) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2011.2143610 · Cited by 473
A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H. (2010) · 2010 IEEE International Solid-State Circuits Conference - (ISSCC) · doi:10.1109/isscc.2010.5433967 · Cited by 96
Metadata
- Authors
- Giannini, V., Nuzzo, P., Chironi, V., Baschirotto, A., Van der Plas, G., & Craninckx, J.
- Venue
- 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
- Publisher
- IEEE
- Published
- 2008-02
- Pages
- 238-610
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2077839561
- Cited by
- 191
- References
- 0
- FWCI
- 52.35
- Type
- conference paper
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. https://app.cochat.ai/papers/10.1109/isscc.2008.4523145
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- Giannini, V., Nuzzo, P., Chironi, V., Baschirotto, A., Van der Plas, G., & Craninckx, J. (2008). An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers. https://doi.org/10.1109/isscc.2008.4523145
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