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19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology
Abstract
Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (8Gb) were accompanied by relatively low read and write performance [1-5]. This work describes a 16Gb ReRAM designed in a 27nm node, with a 1GB/s DDR interface and an 8-bank concurrent DRAM-like core architecture. High parallelism, a pipelined data-path architecture and innovations such as concurrent set/reset verify combine to achieve 200MB/s write and 1GB/s read throughputs in a high-density device.
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Cited by
The future of electronics based on memristive systems
Zidan, M. A., Strachan, J. P., & Lu, W. D. (2018) · Nature Electronics · doi:10.1038/s41928-017-0006-8 · Cited by 2,138
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Song, L., Qian, X., Li, H., & Chen, Y. (2017) · 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2017.55 · Cited by 833
A review of emerging non-volatile memory (NVM) technologies and applications
Chen, A. (2016) · Solid-State Electronics · doi:10.1016/j.sse.2016.07.006 · Cited by 668
Emerging Memory Technologies: Recent Trends and Prospects
Yu, S., & Chen, P.-Y. (2016) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2016.2546199 · Cited by 555
Overcoming the challenges of crossbar resistive memory architectures
Xu, C., Niu, D., Muralimanohar, N., Balasubramonian, R., Zhang, T., Yu, S., & Xie, Y. (2015) · 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2015.7056056 · Cited by 340
Metadata
- Authors
- Fackenthal, R., Kitagawa, M., Otsuka, W., Prall, K., Mills, D., Tsutsui, K., Javanifard, J., Tedrow, K., Tsushima, T., Shibahara, Y., & Hush, G.
- Venue
- 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
- Publisher
- IEEE
- Published
- 2014-02
- Pages
- 338-339
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2020003503
- Cited by
- 217
- References
- 0
- FWCI
- 36.16
- Type
- conference paper
- Language
- en
- Open access
- closed
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- The paper
- Fackenthal, R., Kitagawa, M., Otsuka, W., Prall, K., Mills, D., Tsutsui, K., Javanifard, J., Tedrow, K., Tsushima, T., Shibahara, Y., & Hush, G. (2014). 19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). https://doi.org/10.1109/isscc.2014.6757460
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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