Cited by 337Advanced Memory and Neural ComputingLow-power high-performance VLSI designAdvanced Neural Network Applications

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Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications

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Biswas, Avishek, Chandrakasan, Anantha P.·2018·2018 IEEE International Solid - State Circuits Conference - (ISSCC)

DOI 10.1109/isscc.2018.8310397

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Abstract

Convolutional neural networks (CNN) provide state-of-the-art results in a wide variety of machine learning (ML) applications, ranging from image classification to speech recognition. However, they are very computationally intensive and require huge amounts of storage. Recent work strived towards reducing the size of the CNNs: [1] proposes a binary-weight-network (BWN), where the filter weights (wi's) are ±1 (with a common scaling factor per filter: α). This leads to a significant reduction in the amount of storage required for the Wi's, making it possible to store them entirely on-chip. However, in a conventional all-digital implementation [2, 3], reading the wjis and the partial sums from the embedded SRAMs require a lot of data movement per computation, which is energy-hungry. To reduce data-movement, and associated energy, we present an SRAM-embedded convolution architecture (Fig. 31.1.1), which does not require reading the wi's explicitly from the memory. Prior work on embedded ML classifiers have focused on 1b outputs [4] or a small number of output classes [5], both of which are not sufficient for CNNs. This work uses 7b inputs/outputs, which is sufficient to maintain good accuracy for most of the popular CNNs [1]. The convolution operation is implemented as voltage averaging (Fig. 31.1.1), since the wj's are binary, while the averaging factor (1/N) implements the weight-coefficient α (with a new scaling factor, M, implemented off-chip).

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Kang, M., Gonugondla, S. K., & Shanbhag, N. R. (2020) · Springer eBooks · doi:10.1007/978-3-030-35971-3_4 · Cited by 1
Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration
Jiang, Z., Yin, S., Kim, M., et al. (2019) · 2018 52nd Asilomar Conference on Signals, Systems, and Computers · doi:10.1109/ieeeconf44664.2019.9048678 · Cited by 1
Recovery algorithm to correct silent data corruption of synaptic storage in convolutional neural networks
Roy, A., & Ludwig, S. A. (2020) · International Journal of Hybrid Intelligent Systems · doi:10.3233/his-200278 · Cited by 1
Block-LMS and RLS adaptive filters using in-memory architectures
Radhakrishnan, C., & Gonugondla, S. K. (2020) · 2018 52nd Asilomar Conference on Signals, Systems, and Computers · doi:10.1109/ieeeconf51394.2020.9443414 · Cited by 1
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Chiang, C.-Y., Hu, C.-L., Chang, K.-Y., et al. (2022) · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design · doi:10.1109/smacd55068.2022.9816200 · Cited by 1
Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications
Hong, H.-C., Lin, L.-Y., & Chen, B.-C. (2023) · doi:10.1109/icmts55420.2023.10094078 · Cited by 1
A Main/Subsidiary Network Framework for Simplifying Binary Neural NetworkPreprint
Xu, Y., Dong, X., Li, Y., & Su, H. (2018) · arXiv (Cornell University) · doi:10.48550/arxiv.1812.04210 · Cited by 1
An 8T and 10T static random access memory with bit-serial operations for in-memory computingPreprint
Xu, W., Lou, M., Li, L., Zhang, K., & Gong, L. (2023) · Research Square · doi:10.21203/rs.3.rs-3758835/v1 · Cited by 1
BINAREYE: Digital and Mixed-Signal Always-On Binary Neural Network Processing
Moons, B., Bankman, D. J., & Verhelst, M. (2018) · Springer eBooks · doi:10.1007/978-3-319-99223-5_6
Hardware-Algorithm Co-optimizations
Moons, B., Bankman, D. J., & Verhelst, M. (2018) · Springer eBooks · doi:10.1007/978-3-319-99223-5_3
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Yeo, I., Gi, S.-G., Kim, J.-G., et al. (2019) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas.2019.8771576
In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML ApplicationsPreprint
Kumar, A., Singh, J., Beeraka, S. M., & Gupta, B. (2020) · arXiv (Cornell University) · doi:10.48550/arxiv.2005.09526
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Chung, C.-C., Zhang, H., Hung, M.-Y., et al. (2020) · IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) · doi:10.1109/icce-taiwan49838.2020.9258082
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Kim, J.-H., Seo, B., Oh, Y. H., Chun, J., Lee, J. W., & Kim, J. (2020) · IEEE Access · doi:10.1109/access.2020.3047948
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Yoo, T., Kim, T. T.-H., Kim, B., et al. (2020) · International SoC Design Conference · doi:10.1109/isocc50952.2020.9332992
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Yang, J., Cui, X., Jia, S., & Wang, Y. (2021) · China Semiconductor Technology International Conference (CSTIC) · doi:10.1109/cstic52283.2021.9461459
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Ren, E., Luo, L., Liu, Z., et al. (2020) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc49529.2020.9524791
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Chen, X. (2021) · International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME) · doi:10.1109/iceccme52200.2021.9591078
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Yue, J., Sun, W., Yang, H., & Liu, Y. (2021) · International SoC Design Conference · doi:10.1109/isocc53507.2021.9613846

Authors: Biswas, A., & Chandrakasan, A. P.
Affiliations: Massachusetts Institute of Technology (US)
ORCID: Biswas, Avishek
Chandrakasan, Anantha P.
Venue: 2018 IEEE International Solid - State Circuits Conference - (ISSCC)
Publisher: IEEE
Published: 2018-02
Volume: 2018
Pages: 488-490
ISSN: 0193-6530 (ISSN-L)
DOI: 10.1109/isscc.2018.8310397
OpenAlex: W2792893539
Semantic Scholar: ba28ee795de7c88258053fb31aef198c18b2cd5a
Cited by: 337
References: 7
Citations by year: 2026: 8 · 2025: 13 · 2024: 35 · 2023: 50 · 2022: 55 · 2021: 50 · 2020: 63 · 2019: 50 · 2018: 13
FWCI: 70.19
Type: conference paper
Language: en
Open access: green
hdl.handle.net
Licence: cc-by-nc-sa
Locations: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
DSpace@MIT (Massachusetts Institute of Technology) (submittedVersion, cc-by-nc-sa)
IEEE Conference Proceedings
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
Keywords: data movement reduction

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Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications

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