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Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications
Open accessAbstract
Convolutional neural networks (CNN) provide state-of-the-art results in a wide variety of machine learning (ML) applications, ranging from image classification to speech recognition. However, they are very computationally intensive and require huge amounts of storage. Recent work strived towards reducing the size of the CNNs: [1] proposes a binary-weight-network (BWN), where the filter weights (wi's) are ±1 (with a common scaling factor per filter: α). This leads to a significant reduction in the amount of storage required for the Wi's, making it possible to store them entirely on-chip. However, in a conventional all-digital implementation [2, 3], reading the wjis and the partial sums from the embedded SRAMs require a lot of data movement per computation, which is energy-hungry. To reduce data-movement, and associated energy, we present an SRAM-embedded convolution architecture (Fig. 31.1.1), which does not require reading the wi's explicitly from the memory. Prior work on embedded ML classifiers have focused on 1b outputs [4] or a small number of output classes [5], both of which are not sufficient for CNNs. This work uses 7b inputs/outputs, which is sufficient to maintain good accuracy for most of the popular CNNs [1]. The convolution operation is implemented as voltage averaging (Fig. 31.1.1), since the wj's are binary, while the averaging factor (1/N) implements the weight-coefficient α (with a new scaling factor, M, implemented off-chip).
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“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [32]
Citations
Cites
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
Rastegari, M., Ordonez, V., Redmon, J., & Farhadi, A. (2016) · Lecture Notes in Computer Science · doi:10.1007/978-3-319-46493-0_32 · Cited by 4,408
A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
Moons, B., & Verhelst, M. (2016) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2016.7573525 · Cited by 166
A machine-learning classifier implemented in a standard 6T SRAM array
Zhang, J., Wang, Z., & Verma, N. (2016) · IEEE Symposium on VLSI Circuits (VLSI-Circuits) · doi:10.1109/vlsic.2016.7573556 · Cited by 145
Sim, J., Park, J., Kim, M., Bae, D., Choi, Y., & Kim, L. (2016) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2016.7418008 · Cited by 142
Kang, M., Gonugondla, S. K., Patil, A. D., et al. (2016) · arXiv (Cornell University) · doi:10.48550/arxiv.1610.07501 · Cited by 22
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krishna, K., Rashid, R., & Nambath, N. (2022) · doi:10.36227/techrxiv.19533253
Computing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFET
尹, 勋., 岳, 金., 黄, 庆., 李, 超., 蔡, 嘉., 杨, 泽., 卓, 成., & 刘, 明. (2022) · Scientia Sinica Informationis · doi:10.1360/ssi-2021-0420 · Cited by 1
IoT Regulated Water Quality Prediction Through Machine Learning for Smart Environments
Kaur, E. (2022) · Intelligent systems reference library · doi:10.1007/978-3-030-97516-6_3
Input Conditioned Subranging and Skewed Quantisation of MACs in IMCPreprint
Sundar, A. B., Viraraghavan, J., & Vijayakumar, B. (2022) · doi:10.36227/techrxiv.20330580.v1
Input Conditioned Subranging and Skewed Quantisation of MACs in IMCPreprint
Sundar, A. B., Viraraghavan, J., & Vijayakumar, B. (2022) · doi:10.36227/techrxiv.20330580
YAGAWA, G., & Oishi, A. (2022) · Lecture notes on numerical methods in engineering and sciences · doi:10.1007/978-3-031-11847-0_1
A 65nm 110GOPS 8T-SRAM Computing-in-Memory Macro with Single Cycle Serial Input Mechanism
Li, S., Xu, T., Su, F., Tang, X., & Chen, Y. (2022) · doi:10.1109/iccs56666.2022.9936324
krishna, K., nambath, N., & rashid, R. (2023) · doi:10.36227/techrxiv.19533253.v2
SRAM-based compute-in-memory: status and challenges
Ye, L., Jia, T., Chen, P., Meng, W. U., & Huang, R. (2023) · Scientia Sinica Informationis · doi:10.1360/ssi-2023-0320
A Delta-Sigma Based SRAM Compute-in-Memory Macro for Human Activity Recognition
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Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning
Kim, K. H., & Kang, M. (2024) · International Conference on Electronics, Information, and Communication (ICEIC) · doi:10.1109/iceic61013.2024.10457241
Digital to Pulse Converter for Analog in Memory Compute Applications
Naik, S. B., & Iqbal, A. (2023) · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · doi:10.1109/apccas60141.2023.00025
Yue, J. (2024) · Springer theses · doi:10.1007/978-981-97-3477-1_1
Digital Circuits and CIM Integrated NN Processor
Yue, J. (2024) · Springer theses · doi:10.1007/978-981-97-3477-1_5
Basics and Research Status of Neural Network Processors
Yue, J. (2024) · Springer theses · doi:10.1007/978-981-97-3477-1_2
Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture
Kushwaha, D., Joshi, R., Bulusu, A., & Dasgupta, S. (2024) · IEEE Interregional NEWCAS Conference (NEWCAS) · doi:10.1109/newcas58973.2024.10666330
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Chen, T., Huang, S.-H., Cheng, C.-H., et al. (2024) · doi:10.1109/icce-taiwan62264.2024.10674435
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation
Xiong, T., Ye, Y., Si, X., & Yang, J. (2024) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2024.3439355 · Cited by 1
Pathloth, V., Kavitha, S., & Reniwal, B. S. (2023) · IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) · doi:10.1109/primeasia60757.2023.00016
Sharma, S., Choudhary, G., Gupta, N., et al. (2024) · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · doi:10.1109/apccas62602.2024.10808784
An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units
Lin, Y., Su, L.-Y., & Huang, S.-H. (2024) · International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) · doi:10.1109/ispacs62486.2024.10867960
Design of an SRAM-Based Computing-in-Memory Multiply-Accumulate Circuit for Image Processing
Song, C., Lan, L., Teng, Z., et al. (2025) · doi:10.1109/eicct65471.2025.11100015
Yang, J., Luo, X., Ke, Y., Wang, Z., Shang, H., Dong, S., Fu, Z., Yang, X., Liu, H., & Basu, A. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3638445 · Cited by 2
A Hybrid Computing-in-Memory Architecture for Energy-Efficient Edge AI Inference
Lou, F., DanDan, C. H. E. N., Cao, J., et al. (2025) · International Conference on Integrated Circuits and Microsystems (ICICM) · doi:10.1109/icicm66614.2025.11315955
Lee, J., Park, J., Ahn, C., Jin, H., Lee, S., & Yu, H. (2026) · International Conference on Electronics, Information, and Communication (ICEIC) · doi:10.1109/iceic69189.2026.11386216
In-Memory Computing Paradigm Using Energy-Efficient Analog Arithmetic for DNA Sequence Alignment
Kavitha, S., Reniwal, B. S., & Kailath, B. J. (2026) · IEEE Transactions on Emerging Topics in Computing · doi:10.1109/tetc.2026.3672353
Digital Implementation of Neuromorphic systems using Emerging Memory devices
Hirtzlin, T. (2020) · theses.fr (ABES) · doi:10.70675/7c42d7b9z4001z4424z8a0az6c7cb2079ec8
Towards a new insight of the carbon transport in the global ocean
Ricour, F. (2023) · theses.fr (ABES) · doi:10.70675/6b0e91c7zd2ebz4dfaza925z8de56d803e02 · Cited by 7
Dong, K., Huang, K., Luo, T., et al. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3689154
A Performance-Driven Digital Computing-in-Memory Compiler with LLM Assisted Analysis Method
Cai, W., Chen, X., Chen, J., Ye, Z., Yu, Z., & Zhu, X. (2026) · China Semiconductor Technology International Conference (CSTIC) · doi:10.1109/cstic68613.2026.11537588
Hariprasad, S., Balasubramanian, S., Patel, A. A., & Choi, K. (2026) · Electronics · doi:10.3390/electronics15122630
Mixed-Mode ReRAM Architecture with Digital Weights and Inputs for High-Precision In-Memory Computing
Krishnan, N., Joshi, R. V., & James, A. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562957
Liu, T., Ren, E., Zhu, G., et al. (2026) · Circuits Systems and Signal Processing · doi:10.1007/s00034-026-03699-9
Metadata
- Authors
- Biswas, A., & Chandrakasan, A. P.
- Affiliations
- Massachusetts Institute of Technology (US)
- Venue
- 2018 IEEE International Solid - State Circuits Conference - (ISSCC)
- Publisher
- IEEE
- Published
- 2018-02
- Volume
- 2018
- Pages
- 488-490
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2792893539
- Semantic Scholar
- ba28ee795de7c88258053fb31aef198c18b2cd5a
- Cited by
- 337
- References
- 7
- Citations by year
- 2026: 8 · 2025: 13 · 2024: 35 · 2023: 50 · 2022: 55 · 2021: 50 · 2020: 63 · 2019: 50 · 2018: 13
- FWCI
- 70.19
- Type
- conference paper
- Language
- en
- Open access
- green
- hdl.handle.net
- Licence
- cc-by-nc-sa
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- DSpace@MIT (Massachusetts Institute of Technology) (submittedVersion, cc-by-nc-sa)
- IEEE Conference Proceedings
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Keywords
- data movement reduction
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